QuartusII design partion and logic lock

Design partion

Design partion is often used in "gain variable (qic)". The design partition is used to perform "logical partitioning" on the submodule. The most important setting in the design partition window is netlist type, it has four optional values: source file, post-synthesis, post-fit, and empty (for example, marked 1, 2, 3, and 4 in Chinese, to fully display each type, rather than final setting ). Their respective meanings are:

Source File: if the source code is not modified, only analysis is performed again and synthesis and fitter are required;

Post-Synthesis: if the source code is not modified and you do not need to re-analyze or synthesis, the result will only be fitter;

Post-fit: if the source code is not modified, the results of the previous analysis, synthesis, and Fitter will be retained;

Empty: flag is an empty area. This partition is ignored during compilation.

So we can understand,In fact, to achieve the purpose of "incremental compilation", you only need to set each sub-module in design partition and set the modules that have not been modified to post-fit, the modified module is set to source file. Note that the top-level module status must also be set to post-fit.

 

Reasonable partition Creation)

In us II, any design module at any level in the design can be used as a design partition. A design can also contain more than one design partition, even at the same level of design, you can also have multiple partitions. At the same time,Note: There is no hierarchical relationship between partitions. Any logic can belong to only one partition.Taking Figure 5 as an example, module A consists of three sub-modules: A1, B1, and C1. If module A is set as a partition, Quartus uses the module name to name this partition: partition. Partition A contains all the logic of the sub-modules A1, B1, and C1. However, if the B1 submodule is also created as a partition, partition a contains only the logic of the A1 and C1 submodules, the logic of the B1 submodule only belongs to the new B1 partition.

For a multi-level complex design that contains multiple functional modules, there can be many ways to set partitions. Note that:Not any partition solution can save Compilation Time. Poor design partitions can even cause compilation failure!How can we get an efficient and reasonable design partition? We needFollow these principles::

A.Do not create too many partitions. In general design, we recommend that you set the number of partitions to 4 ~ Between 8;

B.Do not create too small partitions. Generally, we recommend that you do not have less than 1000 le Or Alm;

C.The peripheral interface logic and kernel processing logic are placed in different design partitions;

D.Peripheral interfaces with the same or similar functions can be placed in the same partition if the pin position is adjacent. Otherwise, different design partitions are created;

E.In different partition schemes, it is better to have fewer connections between partitions.

 

 

Exported partition file (. qxp)

 

From the security perspective, we often want to ensure the privacy of our design. An effective method is to use quartuⅱ exported partitionfile (. qxp) to create a network Table file for integrated or layout cabling (excluding source code. This incremental compilation feature requires the support of a complete quartuⅱ license (for example, not supported by a free web version ).

A. Generate a qxp File

1. Integrate the first project;

2. Set the modules to be locked: set as design partition, netlist type (source file), and then perform the second synthesis;

3. Modify the netlist type to post-fit, and then perform the third synthesis;

B. Export the qxp File

1. Export design partition: export the qxp file of the lock module;

C. Import the qxp File

1. Replace RTL code with the qxp file;

2. inport design partition: import the qxp File

3. Just integrate it.

 

Logic lock

　　Logiclock is used to perform "Physical partitioning" on the design. logiclock has two main parameters in windows. Size and state: size have two options: auto and fixed; the State also has two options: Locked and floating. However, there are not four combinations, but there are only three states:

First, auto + floating: the compiler automatically selects the region size and position (displayed by dotted lines in the chip planner)

2. Fixed + floating: the location selected by the compiler, but the size of the region is set by the user. (It is displayed by the short line in the chip planner)

Third, fixed + locked: the size and location of the region are set by the user. (Display on chip planner by solid line)

So what is the role of logiclock in incremental compilation?You still need to emphasize that logiclock is not required for incremental compilation. However, we recommend that you use logiclock for incremental compilation!

 

QuartusII design partion and logic lock