Questions about VGA display experiment

Today I did a VGA display experiment, but the 25 m clock is incorrect, so no image is generated. The initial program is as follows:

The timing sequence is displayed during simulation, but it is incorrect when the hardware is downloaded. The result is correct. In addition, the results of edge-based triggering and level-based triggering for frequency division are different. The following is a VGA experiment that uses adv7123 on the de115 platform. The horizontal and field synchronization signals of 640*480 * m can be calculated based on the VGA timing diagram. Top-level file: // This Is About VGA test results the entire screen is red module VGA (clk_50m, vga_r, vga_g, vga_ B, vga_clk, kernel, vga_blk_n, vga_vs, vga_hs ); input clk_50m; // The input time clockoutput [] vga_r; // output red pixoutput [] vga_ B; // blue pixoutput [] vga_g; // green pix output vga_clk; // adc7123 time clockoutput vga_sync_n; // synchronous signal output vga_blk_n; // blanking signal output vga_hs; // Horizontal synchronization output vga_vs; // field synchronization // wire clk_25m; // pll_25m; U1 (clk_50m, clk_25m); Reg COUNT = 0; // Reg clk_25m;/* [email protected] (posedge clk_50m) Begin count <= count + 1; if (count) clk_25m <= ~ Clk_25m; end */wire clk_25m; [email protected] (posedge clk_50m) Begin count <= count + 1; end assign clk_25m = count; distinct vga_test (clk_25m, vga_r, vga_g, vga_ B, vga_clk, vga_sync_n, vga_blk_n, vga_vs, vga_hs ); endmodule // module vga_contral (clk_25m, vga_r, vga_g, vga_ B, vga_clk, kernel, vga_blk_n, vga_vs, vga_hs); input clk_25m; // The input time clockoutput [] vga_r; // outpu T red pixoutput [] vga_ B; // blue pixoutput [] vga_g; // green pix output vga_clk; // adc7123 time clockoutput vga_sync_n; // synchronous signal output vga_blk_n; // blanking signal output Reg vga_hs; // Horizontal synchronization output Reg vga_vs; // field synchronization // horizontal parameter h_sync_cyc = 95; parameter h_sync_back = 48; parameter h_sync_act = 635; parameter h_sync_front = 15; parameter h_sync_total = 793; // vertical parameter v_sync_cyc = 2; parameter v_sync_back = 33; parameter v_syn C_act = 480; parameter v_sync_front = 10; parameter v_sync_total = 525; parameter h_start = h_sync_cyc + h_sync_back; parameter v_start = Lower + v_sync_back; Reg [] hcount = 0; reg [9:0] vcount = 0; assign vga_r = (hcount> = h_start) & (hcount <= h_start + h_sync_act) & (vcount> = v_start) & (vcount <v_start + v_sync_act ))? 200:0; assign vga_g = (hcount> = h_start) & (hcount <= h_start + h_sync_act) & (vcount> = v_start) & (vcount <v_start + v_sync_act ))? 0: 0; assign vga_ B = (hcount> = h_start) & (hcount <= h_start + h_sync_act) & (vcount> = v_start) & (vcount <v_start + v_sync_act ))? 0: 0; assign vga_clk = clk_25m; assign Signature = 1' B0; assign Signature = vga_hs & vga_vs; [email protected] (posedge clk_25m) begin if (hcount

Questions about VGA display experiment