"FPGA whole step---actual combat drill" fifth chapter based on 74hc595 led operation

1 Basic Theory Section 1.1 Frequency

Crossover, yes, this concept is also important. Frequency division refers to a single frequency signal is reduced to the original 1/n, called N-division. The realization of the frequency divider circuit or device called "divider", such as the 33MHZ signal 2 to get 16.5MHZ signal, 3 to get 11MHZ signal, 10 to get 3.3MHZ signal.

Frequency division is mainly relative Yu Shijing vibration, with less than that high frequency, the Development board generally according to the specific needs will be added crystal oscillator, generally if the power consumption is higher can choose 50MHz, other conditions can be relatively adjusted, such as 24MHz and so on. So the typical application of frequency division, two-way, four-way, eight-way, there is any crossover.

For the crossover, we can use the Quartus II comes with the PLL to divide, this will occupy a certain amount of resources, you can also use the counter to achieve a certain frequency division, note that the FPGA is different from other CPUs, there is no concept of timers, only counters.

1.2 LED

LED (Light emitting diode), LEDs, or LEDs, is a solid-state semiconductor device capable of converting electrical energy into visible light, which can be converted directly into optical. Can be used in the circuit and the instrument as the indicator light, or composed of text or digital display. There are different compounds made of diodes such as arsenic, gallium, phosphorus and other compounds made, different combinations of compounds will show different colors of light.

In the design of LED driver circuit, can not directly receive 3.3V or 5V to light, LED has rated current, more than this rated current, LED will burn off, reverse will also burn. The average LED's rated current ranges from 10ma~1a. FPGA development uses the LED is mainly SMD 0805 or 0603, etc., the rated circuit generally from 10ma~30ma.

1.3 74HC595

The LED control on the board is the 74hc595 chip of the shift register which is strung in and out/strung out, the chip is shown in the connection condition 5.1 of the circuit, and the physical figure 5.2 shows. Where the Mr Pin is directly connected to the high level without resetting. The string out pin 9 is not connected and does not use the serial pin. The output enable pin 13 is directly grounded and is recommended in the manual. The 11 and 12 pins are the shift register clock input and the memory clock input, respectively.

Figure 5.1 LED part circuit diagram

Figure 5.2 Physical diagram

2 Verilog Code Implementation Section 2.1 74HC595 Control Section

The 14 row defines a global parameter, Width = 8, that is used to control all the use of quantities below.

59 rows and 60 lines respectively define the clock signal and clock enable signal, wherein the clock signal SCLK the first half of the clock period is low, the second half is high, you can achieve intermediate sampling of the data, clock enable signal led_time can control the data and clock alignment. The state of the 48 row is a register of status changes, which is valid as long as the data is updated.

The 75 row defines the update_input signal used to detect changes in the input data.

The state transition section, in the case statement first detect the initial state of the bit, and then into the loop operation, detect whether update_input enable, enable update state, do not allow to maintain state, updated after the start output bit counter led_cnt count

In 121 to 123 lines, the output of the three-way signal constraints, the value of this method of reference, in the use of the output signal, when used to output signal, the most significant savings in the clock. The led_data_out is first output from high to low.

2.2 LED Data Generation Section

At the module declaration, a global definition variable is still used to control the use of constants in the module.

A counting module that generates a clock enable signal.

Reg-type variable led_out_cnt is used to control the LED change, whenever the clock signal enable to start counting, the board has a total of 8 LEDs, so Count 8.

LED decoding part, through the above led_out_cnt signal decoding, control led running water operation.

3 Modelsim Verification Part 3.1 led_generate module emulation

The 43 line generates a clock signal, which is controlled through the period cycle. The 49~51 generates a reset signal, and the reset signal is pulled higher when the clock drops two times. 56 lines are used to monitor the time of the led_out output, as shown in the generated script file 5.3.

Figure 5.3 Simulation Waveform

Figure 5.4 is the use of script file generation, you can observe the realization of the flow function, and the time interval of 1s;

Figure 5.4 Script Generation file

3.2 led_74hc595 module emulation

The first half and the above are the same, can be used as a fixed part, you can copy themselves. 59 rows to 63 lines increase the initialization of the system input signal. Before entering the input signal, it is best to have the most secure initialization.

Lines 75 to 87 are analog inputs to the input, and monitor the led_data-out signal, the output of the results of 5.5, shown by the graph can be seen in the interval of 120ns.

Figure 5.6 is the simulation waveform, you can see the clock led_sclk each sampling in the positive middle position of the input signal, to maximize the reliability of the sampling.

Figure 5.5 Script file

Figure 5.6 Simulation Waveform

"FPGA whole step---actual combat drill" fifth chapter based on 74hc595 led operation