"Xilinx-lvds Read and write function implementation"-00-start

Recently used an LVDS interface camera, 640*480 grayscale image, data rate of 600Mbps, bit width 10bit,ddr double edge sampling.

The implementation of data acquisition needs to use the SerDes module in the FPGA, has now been simulated, and then after the success of the board to write a concrete implementation of ideas, and logical structure.

Mainly includes the function, iserdes of the bilateral along the sampling realization, the iserdes bit synchronization bitslip realization, the image frame synchronization realization, the image data frame to the Axi4-stream bus realization.

"Xilinx-lvds Read and write function implementation"-00-start