Relationship between J-tag and J-Link

To debug arm, you must follow the debugging interface protocol of arm. JTAG is one of them. During simulation, IAR, Keil, ads, and so on all have a common debugging interface. RDI is one of them. How can we complete RDI --> arm debugging protocol (JTAG)? There are two methods:

1. write a service program on the computer, parse the rdi commands in iar, Keil, and ads into the relevant JTAG protocol, and then use the next physical conversion interface (note, this conversion is only the conversion of the electrical physical layer, as it works like RS232) Send your target board. H-JTAG is like this. H-JTAG hardware is just a physical level of the conversion interface, so very simple. The H-JTAG software installed in the computer is the service program mentioned earlier, responsible for protocol conversion.

2. Use this board to directly receive Debugging commands from software such as IAR, Keil, and ads, and convert the RDI-> JTAG protocol. Then communicate with the target board. This is how jlink works.

From the above we can see that the H-JTAG is software for protocol conversion, so the speed is slow, but the hardware is simple. The jlink of the second method generally carries a powerful CPU for hardware protocol conversion, which makes the hardware complex but fast.

 

Basic Principles of JTAG

JTAG (joint test action group) is an international standard test protocol (IEEE 1149.1 compatible ). The standard JTAG interfaces are 4-wire-TMS, tck, TDI, and TDO, which are the mode selection, clock, data input, and data output lines respectively.

JTAG has two main functions:

1) One type is used to test the electrical characteristics of the chip and check whether the chip is faulty;

2) The other type is used for debugging and debugging various chips and their peripheral devices. a cpu containing the JTAG debug interface module, as long as the clock is normal, you can use the JTAG interface to access the internal registers of the CPU, the devices mounted on the CPU bus, and the registers of the built-in modules. This article mainly introduces the debug function.

1. Analysis of JTAG principles

To put it simply, the working principle of JTAG can be summarized as: Define a Test Access Port (Test Access Port) inside the device ), test and debug internal nodes using dedicated JTAG testing tools. First, we will introduce the basic concepts and content of border scan and tap.

1. Border Scan

The basic idea of boundary-scan technology is to add a shift register unit on the input/output pins near the chip, that is, boundary-scan register ).

When the chip is in the debugging status, the boundary scan register can isolate the chip from the peripheral input/output. Through the Boundary Scan register unit, you can observe and control the input/output signals of the chip. For the input pin of the chip, the signal (data) can be loaded into the pin through the connected boundary scanning register unit. For the output pin of the chip, you can also "capture" the output signal on the pin through the connected boundary scanner. In normal operation, the boundary scan register is transparent to the chip, so normal operation will not be affected. In this way, the boundary scan register provides a convenient way to observe and control the chips to be debugged. In addition, the boundary scan (shift) Register units on the chip input/output pins can be connected to each other to form a boundary-scan chain around the chip ). The boundary scan chain can be input and output in serial mode. Through corresponding clock signals and control signals, you can conveniently observe and control the chips in the debugging state.

1. Test the access port tap

The test access port (TAP) is a common port used to access all data registers (DR) and command registers (IR) provided by the chip ). The control of the entire tap is achieved through the TAP controller. Next we will introduce several interface signals of the TAP and their functions. The first four signals are mandatory in the ieee1149.1 standard.

TCK: the clock signal, which provides an independent and basic clock signal for the operation of the TAP.
TMS: Mode Selection signal, used to control the switch of the TAP state machine.
TDI: data input signal.
TDO: data output signal.
Trst: reset signal, which can be used to reset (initialize) the TAP controller ). This signal interface is not mandatory in the IEEE 1149.1 standard, because you can reset the TAP controller through TMS.
Stck: The Clock return signal, which is not mandatory in the IEEE 1149.1 standard.

To put it simply, the PC can debug the target board by accessing the related data registers (DR) and instruction registers (IR) through the tap interface.

After the system powers on, the TAP controller first enters the test-logicreset status, run-test/idle, selcct-DR-scan, select-ir-scan, capture-IR, shift-IR, exitl-IR, and update-IR respectively, finally, return to the run-TCST/idle status. In this process, the status transition is driven by the TCK signal (rising edge), and the status of the tap is switched by the TMS signal. In the capture-Ir state, a specific logic sequence is loaded into the instruction register. In the shift-Ir state, a specific instruction can be sent to the instruction register; in the update-IR status, the command entered in the instruction register is used to update the instruction register. Finally, the system returns to the run-test/idle status, and the command takes effect to complete access to the command register. After the system returns to the run-test/idle status, it selects the required data register based on the content of the preceding command register and starts to execute data register operations. The basic principle is exactly the same as the access to the instruction register, which are seiect-DR-scan, capture-DR, shift-D, exitl-DR, and update-dr, finally, return to the run-TCST/idle status. With tdl and TDO, you can load new data into the data register. After a period, the data in the data register can be captured, and the data on the chip pins connected to each register unit in the data register is updated, and the access to the data register is also completed.

Currently, the JTAG interfaces on the market are 14-pin and 20-pin. Among them, the 20 PIN is the mainstream standard, but there are a few target board uses 14 pin. After simple signal conversion, they can be used in general.

Example:

[, From left to right 1-5 are common 20pin2 in the market. 54 spacing, 20 pin2. 0 spacing, 14pin2. 54 spacing, 10pin2. 0 spacing, 10pin2. 54-margin JTAG port]

The mini2440 arm Development Board uses the 10-pin JTAG interface, while jlink uses the standard 20-pin JTAG. Therefore, you need to create a connection cable with a 20-pin head, the other is a 10-pin head, And the link in the middle is as follows:

10-pin JTAG	20-pin JTAG	Signal
1, 2	1	Vtref
-	2	NC
3	3	Ntrst
-	4	Gnd
5	5	TDI
-	6	Gnd
7	7	TMS
8	8	Gnd
9	9	TCK
10	10	Gnd
-	11	Rtck
-	12	Gnd
6	13	TDO
-	14	Gnd
4	15	Reset
-	16	Gnd
-	17	Dbgrq
-	18	Gnd
-	19	5v-supply
-	20	Gnd

Whether the 10-pin JTAG of other manufacturers can be connected to the 20-pin standard JTAG, please refer to the manufacturer's instructions to confirm each signal line.

 

The mini2440 arm Development Board uses the 10-pin JTAG interface, while jlink uses the standard 20-pin JTAG. Therefore, you need to create a connection cable with a 20-pin head, the other is a 10-pin head, And the link in the middle is as follows:

10-pin JTAG	20-pin JTAG	Signal
1, 2	1	Vtref
-	2	NC
3	3	Ntrst
-	4	Gnd
5	5	TDI
-	6	Gnd
7	7	TMS
8	8	Gnd
9	9	TCK
10	10	Gnd
-	11	Rtck
-	12	Gnd
6	13	TDO
-	14	Gnd
4	15	Reset
-	16	Gnd
-	17	Dbgrq
-	18	Gnd
-	19	5v-supply
-	20	Gnd

Whether the 10-pin JTAG of other manufacturers can be connected to the 20-pin standard JTAG, please refer to the manufacturer's instructions to confirm each signal line.