Repost Reset vector and exception Vector

When setting the CPU parameters during the learning process of the nioshi II, the Reset vector and exception vector settings are encountered. Shows the parameter setting screen.

Reset vector -- Reset vector
Exception vector -- execution Vector
First, it indicates that both vector addresses store programs. The following are explanations.
Reset vector -- Reset vector
When FPGA is reset, FPGA re-executes and re-executes the re-operation. This requires reading the program from the PV. Because FPGA programs are stored in the PVS, the Reset vector is the PV.
Exception vector -- execution Vector
When FPGA is running, the program needs to be read from and stored in the SDRAM before it can operate.
The above principle is the same as that of 51 single-chip microcomputer.

Repost Reset vector and exception Vector