Reprinted and used the position and reset port of the trigger to optimize the design.

The combined logic can be optimized by selecting different register models during design.

In a given device, most FPGA vendors provide various trigger units. For some given logical functions, the integrated tools can usually use the positions and reset ports of triggers, which greatly reduces the burden of table searching. For example, a design logic circuit is shown in 2-11. In this example, the integrated tool can select the position port of the trigger to implement the combined logic function, as shown in Figure 2-12. This reduces the consumption of logic gates and increases the speed of data paths. In the same way, we can see the logic functions shown in 2-13. You can directly connect the input signal to the reset port of the trigger to remove the gate and keep the function unchanged, as shown in 2-14.

 

Figure 2-11: simple synchronization logic with or gate

 

Figure 2-12: or the door is implemented by the position port of the trigger

 

Figure 2-13: simple synchronization logic of the belt and door

 

Figure 2-14: Implemented With the reset port of the trigger

 

If the integrated tool does not use the above optimization means, the root cause is the reset policy adopted in the logic design. Any restrictions on resetting will not only consume resource slots and reset ports, but also restrict the selection of factory library units. Therefore, it is said that the consumption of resource slots and reset ports may prevent the optimization of some combination logics.

 

For example, we will implement the following code on a Spartan-3 device in Xilinx. In this instance code, an external reset signal is used to reset the trigger status, as shown in Figure 2-15.

 

Module setreset (

Output Reg Odat,

Input ireset, iclk,

Input idat1, idat2 );

Always @ (posedge iclk or negedge ireset)

If (! Ireset)

Odat <= 0;

Else

Odat <= idat1 | idat2;

Endmodule

 

Figure 2-15: simple Asynchronous Reset

 

As shown in 2-15, a reset trigger implements an Asynchronous Reset capability. The logic function (OR gate) is implemented by a discrete logic gate. As an alternative, if we remove the reset, but the implemented logic functions remain unchanged, the design will be optimized as shown in 2-16.

 

Figure 2-16: optimization results without resetting

 

In this example, the integrated tool can use the FDS unit (trigger with synchronization slot and reset, flip-flop with a synchronous set and reset) and use its set port to implement logic or operations. Therefore, by allowing the integrated tool to select a trigger with a synchronization location, we can implement the instance function when there is no logical unit consumption.

 

For further discussion, we can also optimize the design by using both the synchronization slot and reset port. For example, if we need to implement the functions shown in the following logical equation:

Odat <=! Idat3 & (idat1 | idat2)

 

We can achieve this through the following hardware code. In this implementation, we can see that the synchronization slot and reset resources are used at the same time.

 

Module setreset (

Output Reg Odat,

Input iclk,

Input idat1, idat2, idat3 );

Always @ (posedge iclk)

If (idat3)

Odat <= 0;

Else if (idat1)

Odat <= 1;

Else

Odat <= idat2;

Endmodule

 

In the above Code, the input idat3 has the same priority as the reset port of the relevant trigger. Therefore, this logic function can be implemented as shown in Figure 2-17.

 

Figure 2-17: using the trigger's position and reset port for Optimization

 

From 2 to 17, according to the preceding Logic Equation, there are three logical operations (inverse, logical and logical or) in this circuit. We can see that all these operations are implemented by one trigger, no query table is consumed. Because these optimizations are not easy to know in the design code phase, when a design area is a key factor, please try to avoid using the trigger's location and reset port.

Reprinted and used the position and reset port of the trigger to optimize the design.