Reprinted Key Path Optimization instances

This example shows how to optimize the design sequence by reorganizing the path. First, let's look at the optimized instance Code provided in the original book.

The following is the code snippet before optimization: Module randomlogica ( Output Reg [7: 0] Out, input [7: 0] A, B, C, input CLK, input cond1, cond2); always @ (posedge CLK) if (cond1) out <= A; else if (cond2 & (c <8) out <= B; elseout <= C; endmodule

The above code is integrated in Quartus II to obtain the result shown in Figure 1. Figure 1: Overall result 1 before optimization shows that the Key Path of the circuit exists between C and out, and goes through a comparator, level 1 and gate, and level 2 multiplexing selector, compared with the original book, although the path passes through the same logic level, the circuit structure may be different. However, the overall circuit functions are not different. Next we will modify the original code to optimize the above key paths. The modified code is as follows:

The following is a code snippet: Module randomlogicb ( Output Reg [7: 0] Out, input [7: 0] A, B, C, input CLK, input cond1, cond2); wire condb = (cond2 &! Cond1); always @ (posedge CLK) if (condb & (c <8) out <= B; else if (cond1) out <= A; elseout <= C; endmodule

The modified code is integrated in QuartusII, as shown in result 2.

 

Figure 2: optimized results

Like the conclusion of the original book, we can compare figure 1 and figure 2 and find that the logical level of the Key Path is reduced to only two levels.

Reprinted Key Path Optimization instances