Sanshu's FPGA Series II: por, configuration, initialization, and resetting in cyclone v

I have been fascinated by the internal resetting of FPGA. I have carefully studied the official data manual over the past two days. I have understood many of my doubts and I feel that I have made some progress .....

I. About POR (power-on Reset)

When FPGA is powered on, it first enters the reset mode, clears all Ram bits, and sets user I/O to three States through the internal weak pull-up resistor. The configuration and initialization are completed in sequence. If all the operations are successful, the FPGA enters the user mode and starts to work according to the time sequence logic written by the user.

Ii. Detailed FPGA power-on Process

From the first article, we know that there is a process from FPGA power-on to entering the user mode. Don't put the time sequence chart, it's disgusting. Just pick it up, as shown in 1.

Figure 1

Detailed Process

1. A reset event is triggered when power-on is enabled. The nconfig, nstatus, conf_done, and init_done pins are lowered to clear the ram bit. The three-state user I/O enters the reset;
2. During the reset process, the control logic detects all the power supply voltages. when they reach the specified value at the specified time and stabilize, the configuration is entered, otherwise, you need to reset nconfig to wait for the voltage to reach the standard. Excellent power supply design is very important for digital circuits;
3. After the reset is completed successfully, nconfig and nstatus will be released in turn, so that they are pulled up by the pull-up resistor to enter the configuration. The configuration mode must match the setting of msel, the logic circuit is compiled by Quartus to generate a configuration file. At this time, it is written to FPGA. This process is called configuration. Common configuration methods include JTAG online mode and EPC/epcq configuration mode;
4. After the configuration is successful, conf_done is released and initialized. The registers are set to the expected values according to the user's intention;
5. After Initialization is complete, init_done is released to enter the user mode, and the system starts to run according to the specified sequence.

 

* ***** Note *****

• The power supply is unstable. There is no need to talk about it in the future. The power supply quality is good, and everything should be smooth in the future;
• When designing the hardware circuit, nconfig, nstatus, and conf_done must be pulled up. Everything is fine after initialization, so init_done does not need to be concerned. After the configuration is complete, it will be used as a common I/O;
• Msel [4: 0] settings;
• When designing the hardware circuit, you should pay attention to configuring the flash and FPGA connection, and the JTAG port design. If the hardware is wrong, the white blind;

Iii. FPGA Reset

As mentioned above, we know that FPGA must be reset, initialized, and other operations each time it is powered on. Therefore, in theory, FPGA does not need to be reset in subsequent work projects, especially global reset. However, on the one hand, local reset and register initialization (assign values at any time during the time series) should be performed to ensure that the values in the registers are our expected values, in addition, some IP cores must be reset before they work. On the other hand, it is inevitable that the sub-Steady State occurs in the circuit to cause system operation exceptions. This requires a mechanism to trigger a reset event, enable the system to go to "reset-> Configuration-> initialization-> User Mode.

So there are:

1. As mentioned in the article "one of the three uncles FPGA Series: clock resources in cyclone V", global clock cabling resources are usually very limited, and global reset uses global clock cabling resources, therefore, you can use local reset instead of global reset. That is, do not use the same rst_n in all always. Multiple Local reset signals rstn0 can be generated through internal logic, rstn1, rstn2 .....
2. In hardware circuit design, FPGA before Cyclone V has reset pins, but the Design Manual does not say that this pin must be used for resetting and can be used as a common I/O, the reset pin is canceled in cyclone v. My understanding is: the reset pin has two functions. One is to trigger a reset event such as a manual button when an exception occurs during system operation so that the system can be reset; second, the capacitor delay method is used to forcibly increase the power-on reset time to ensure successful reset. When there is no need for both sides of the appeal, the reset pin is useless, so intel niub directly removes the reset pin in cyclone V (Personal conjecture, not approved in the technical area );
3. Again, reset = Global reset. There are 10 thousand global reset methods, such as using internal logic or using MATLAB to control serial ports;
4. There are different opinions on whether to use global reset. Intel has no official statement on the Internet. My understanding is to look at my personal system. For example, if the global clock is insufficient, pass global reset and use local reset. Otherwise, the resource is sufficient and the global reset is used.

4. Update after verification

Many of the content in section 3 is my personal conjecture, but I also refer to the official manual and personal project development experience, with an accuracy of. I will update it after subsequent verification.

 

Sanshu's FPGA Series II: por, configuration, initialization, and resetting in cyclone v