Scenario analysis of OR1200 data cache application

The following excerpt, "Step fright Core-the interior design and analysis of the soft-core processor," a book

13.7DcacheOne of the use scenarios--storage instruction Run phaseDcacheTarget loss

Storage instruction Run Phase Dcache lost target such a situation in the way of writing, back to the wording of the strategy has a different running process, in the written strategy directly write the corresponding address in the memory, do not operate Dcache.

Under writeback policy. First infer whether the line of the folder table in the corresponding dcache of the destination address is altered, assuming (Dirty is 1). Write the line back into memory, then read the memory block of the destination address into the Dcache, populate it with the corresponding line, and then change the data in the corresponding destination address in the dcache . Assuming that the corresponding line of the destination address has not been altered (Dirty is 0), then directly read the memory block of the destination address into the Dcacheand populate the corresponding line , and then change the data for the corresponding destination address in Dcache .

What 13.7 see.

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(The text of the detailed analysis process reference book)

13.8 DcacheUse scenario two--storage instruction Run phaseDcacheHit

Storage instruction Run phase Dcache hit such a scenario in the way of writing, back to the wording of the strategy also has a different running process, in the strategy, write Dcache in the folder table corresponding line, but also write the corresponding address in memory , in the writeback strategy, just write the dcache in the folder table corresponding to the line. What 13.11 see.

(The text of the detailed analysis process reference book)

13.9 DcacheUse Scenario three--L.MTSPRInstruction WriteDcacheSpecial registers in

DcacheThere are three special registers:Dcbir、Dcbfr、DCBWR, its role in13.3Section has been described. From the code analysis, it can be found that, under the method of writing, only the use ofDcbir、Dcbfr。 All three special registers can be used under the writeback strategy. This is also very well understood, in the way of writing strategies.DcacheIn the folder table LineThe flag bitDirtyAlways for0。 SoDcbir、DcbfrThe role is the same. And it's not necessarily there.DCBWRRegister, so this chapter will instructL.MTSPRWriteDcacheSpecial registers in this scenario are divided into four scenarios such as the following:

(1) under the wording strategy. Instruction L.mtspr write dcbir,dcbfr

(2) back to the writing strategy, instruction L.MTSPR write Dcbir

(3) back to the writing strategy, instruction L.MTSPR write DCBWR

(4) back to the wording strategy. Instruction L.mtspr write dcbfr

(The text of the detailed analysis process reference book)

13.10 DcacheAnalysis Summary

Dcache has a variety of usage scenarios, and this chapter only analyzes three of them, but that's enough for us to understand Dcache 's work process. The process for the rest of the scenario is similar to this. I personally feel that the dcache module is the most complex module in OR1200 , due to the loading, storage instructions, but also to consider the use of writing strategy is to write, back to the wording, but also to consider the Dcache in the corresponding folder items of the flag bit V,Dirty , so it's very complicated.

For this At the end of this chapter, respectively, in the way of writing, back to the wording. dcache Work flow chart,13.18,13.19 , which also gives the DC_FSM module in the finite state machine between the various states of the conversion situation.

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Scenario analysis of OR1200 data cache application