Solution to clock control and multiple fan-out problems

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In FPGA design, wiring problems caused by unreasonable design often occur.Clock Control and multi-fan out problems.

The clock isYou do not need to use the global clock resource bufg in FPGA to control the trigger clock along the input end.InsteadThe signal generated by the combination logic and other time series logic (such as the divider) is used as the trigger clock along the input end.. The Clock is easy to cause clock drift and glitch, making the trigger operate by mistake. Generally, the compiler canAutomatically route distributed clock BuffersBut for the clock with many driver triggersUnstable WiringSevere customers cause design chaos. The entire designReduces the maximum working speed and reduces product performance..

The usual solution to the clock gate problem isConverts the divider into a pulse signal with a cycle width of the system clock width.The so-called system clock is a high-fan-out, zero-drift, and zero-distortion clock resource driven by the global clock resource bufg. The layout structure inside FPGA is a tree structure.

Sends the output of the divider to the CE end of the trigger. When the system clock arrives, it checks the effectiveness of the CE signal. When the CE signal is valid, it changes the output of the trigger, it works exactly the same as the divider,

In addition, this makes cabling more optimized. (Enable clock)

ForMultiple fan outletsGenerally, a node is used to drive multiple lower-level logical devices.

Multiple triggers can also be classified as such problems. This problem will seriously affect the stability of FPGA wiring.

Note thatCopy register policy:

CLK is the system clock, and m1 is a 1 MHz square wave signal. Because there are many modules driven by M1 signal, M1 fan out is

Multiple (assuming that the number of Fan outputs is 140). To reduce fan outputs, use the system clock to sample and drive the M1 signal to seven d triggers,

Then, seven d triggers are distributed to seven modules at the output end, so that each replication point (dup0 ~ Dup6) the average fan output is 20,

The fan-out of M1 signal is changed to 7, which reduces the fan-out of each signal,Optimized the logic and improved the overall design.

Performance.

The following is a description of the above-mentioned module in VHDL:

Library IEEE;
Use IEEE. std_logic_00004.all;
Entity regdup is
Port (
CLK: In std_logic;
DUP: Out std_logic_vector (6 downto 0 );
M1: In std_logic );
End regdup;

Architecture RTL of regdup is
Begin
Process (CLK)
Begin
If CLK 'event and CLK = '1' then -- system clock sampling
DUP (0) <= m1; -- Copy M1 Signal
DUP (1) <= m1;
DUP (2) <= m1;
DUP (3) <= m1;
DUP (4) <= m1;
DUP (5) <= m1;
DUP (6) <= m1;
End if;
End Process;
End RTL;