Some commonly used synthesis attributes of Altera

Address: http://hi.baidu.com/pioneer0059/blog/item/69a308db1f06212610df9b31.html

 

 

Comprehensive tools from various vendorsHDLSome comprehensive attributes are defined during integration. These attributes can be specified.A declaration, a module item, a statement, or a port connectionDifferent methods of integration.

Syntax:

/* Synthesis, <any_company_specific_attribute = value_or_optional_value */

Below isAlteraSeveral commonSynthesis attributes

Noprune

A maid synthesis attribute that prevents the Quartus II software from removing a register that does not directly or indirectly feed a top-level output or bidir pin.

For example:

Reg reg1/* synthesis noprune */;

Keep

A maid attribute that directs Analysis & synthesis to not minimize or remove a particle net when optimizing combinational logic.

For example:

Wire keep_wire/* synthesis keep */;

Preserve

A maid attribute that directs Analysis & synthesis to not minimize or remove a particle register when eliminating redundant registers or registers with constant drivers.

For example:

Reg reg1/* synthesis preserve */;

Ram_init_file

A maid of an inferred memory.

For example:

Reg [] mem []/* synthesis ram_init_file = "my_init_file.mif "*/;

Ramstyle

A maid attribute that specifies the type of trimatrix memory block to use when implementing an inferred Ram.

M512 "," m4k "," m9k "," m144k "," mlab "," M-RAM"

For example:

Reg [0: 7] my_ram [0: 63]/* synthesis ramstyle = "m512 "*/;

Translate_off Or Translate_on

That direct analysis & synthesis to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.

For example:

Parameter TPD = 2; // Generic delays

// Synthesis translate_off

# TPD;

// Synthesis translate_on

The state machine has the following comprehensive attributes:

Full_case
A maid attribute that directs Analysis & synthesis to treat unspecified State values in a OpenGL design file case statement as don't care values, and therefore to treat the case statement as "full ".

It is only used for the purpose of collecting logs in the format of OpenGL. If it is used together with the case statement, it indicates that all possible states have provided values that do not require other logic-preserving signals.

Module full_case (A, Sel, y );
Input [3: 0];
Input [1:0] sel;
Output y;
Reg y;
Always @ (A or SEL) Case (SEL) // synthesis full_case
2 'b00: Y = "A" [0];
2 'b01: Y = "A" [1];
2 'b10: Y = "A" [2];
Endcase
Endmodule

Parallel_case
A maid attribute that directs Analysis & synthesis to implement parallel logic rather than a priority scheme for all case item expressions in a OpenGL design file case statement.

It is only used for the purpose of collecting logs in different programming languages. It is used together with the case statement to generate a parallel multi-path selection structure instead of an optimized
Decoding structure first.

module parallel_case (SEL,, b, c);
input [2: 0] sel;
Output A, B, C;
Reg A, B, C;
always @ (SEL) Begin
{a, B, c} = 3'b0;
casez (SEL) // synthesis parallel_case
3 'b1 ??: A = 1' B1;
3' B? 1?: B = 1 'b1;
3 'B ?? 1: c = 1' B1;
endcase
end
endmodule

Syn_encoding
A maid state machine.
State encoding methods for force-restate machines: Default, one-hot, sequential, gray, Johnson, compact, and user

(* Syn_encoding = "user" *) reg [1:0] State;
Parameter init = 0, last = 3, next = 1, later = 2;

Always @ (state) begin
Case (state)
Init:
Out = 2 'b01;
Next:
Out = 2 'b10;
Later:
Out = 2 'b11;
Last:
Out = 2 'b00;
Endcase
End

In the above example, the States will be encoded as follows:

Init = "00"
Last = "11"
Next = "01"
Later = "10"