Some Questions about stm32 enable (setena; clrena)

Recently, due to the reasons for the national competition, I started to learn stm32 and read incomplete manuals and M3 authoritative manuals. There are some problems. Regarding setena and clrena, both of them can only write 1 and 0 will be invalid, at the same time, both of them are readable and writable. Since they are readable, what they read should be meaningful and regular, and it should be able to reflect the enable state of interruption, otherwise, the hardware designer has no reason to design this item as readable. So I was thinking, assuming that I first write one to the Enable bit and then write one to the Division energy, what should the Enable bit be at this time? Theoretical speculation should be 0; this should be a feedback mechanism; (no relevant information is found on the internet, and M3 is not very detailed, so it can only be guessed at this time ), however, the following program simply verifies the feedback mechanism of this conjecture.

# Include "sys. H "# include" delay. H "# include" usart. H "# define setena0 (* (volatile unsigned long *) 0xe000e100) # define clrena0 (* (volatile unsigned long *) 0xe000e180 )) # define setpend0 (* (volatile unsigned long *) 0xe000e200) # define clrpend0 (* (volatile unsigned long *) 0xe000e280) int main (void) {// unsigned long T1 = 0; // unsigned long T2 = 0; pai_clock_init (9); delay_init (72); uart_init (72,960 0 ); // setena0 = 0x00080000; // setena0 = 0x00000000; // clrena0 = 0x00080000; // setena0 = 0x00080000; // setpend0 = 0x00040000; // setpend0 = 0x00000000; // clrpend0 = 0x00040000; // setpend0 = 0x00040000; // delay_ms (10); printf ("process1: \ n "); printf (" input-: \ tsetena0: 0; \ tclrena0: 0 \ n "); delay_ms (10); setena0 = 0x00000000; clrena0 = 0x00000000; printf ("setena0: % lx \ n", setena0); printf ("clrena0: % lx \ n", clrena0); printf ("process2: \ n "); printf (" input-: \ tsetena0: 0; \ tclrena0: 1 \ n "); delay_ms (10); setena0 = 0x00000000; clrena0 = 0x00080000; printf ("setena0: % lx \ n", setena0); printf ("clrena0: % lx \ n", clrena0); printf ("process3: \ n "); printf (" input-: \ tsetena0: 1; \ tclrena0: 0 \ n "); delay_ms (10); setena0 = 0x00080000; clrena0 = 0x00000000; printf ("setena0: % lx \ n", setena0); printf ("clrena0: % lx \ n", clrena0); printf ("process4: \ n "); printf (" input-: \ tsetena0: 1; \ tclrena0: 1 \ n "); delay_ms (10); setena0 = 0x00080000; clrena0 = 0x00080000; printf ("setena0: % lx \ n", setena0); printf ("clrena0: % lx \ n", clrena0 ); /*** switch order */printf ("switch the case: \ n ************************ \ n "); printf (" process5: \ n "); printf (" input-: \ tclrena0: 0; \ tsetena0: 0 \ n "); delay_ms (10); clrena0 = 0x00000000; setena0 = 0x00000000; printf ("setena0: % lx \ n", setena0); printf ("clrena0: % lx \ n", clrena0); printf ("process6: \ n "); printf (" input-: \ tclrena0: 0; \ tsetena0: 1 \ n "); delay_ms (10); clrena0 = 0x00000000; setena0 = 0x00080000; printf ("setena0: % lx \ n", setena0); printf ("clrena0: % lx \ n", clrena0); printf ("process7: \ n "); printf (" input-: \ tclrena0: 1; \ tsetena0: 0 \ n "); delay_ms (10); clrena0 = 0x00080000; setena0 = 0x00000000; printf ("setena0: % lx \ n", setena0); printf ("clrena0: % lx \ n", clrena0); printf ("process8: \ n "); printf (" input-: \ tclrena0: 1; \ tsetena0: 1 \ n "); delay_ms (10); clrena0 = 0x00080000; setena0 = 0x00080000; printf ("setena0: % lx \ n", setena0); printf ("clrena0: % lx \ n", clrena0 ); // printf ("setpend0: % lx \ n", setpend0); // printf ("clrpend0: % lx \ n", clrpend0);/* While (1) {printf ("T: % d \ n", T); delay_ms (500); t ++ ;}*/}

The following is the result of serial port debugging:

process1:INPUT-:         SETENA0:0;      CLRENA0:0SETENA0:0CLRENA0:0process2:INPUT-:         SETENA0:0;      CLRENA0:1SETENA0:0CLRENA0:0process3:INPUT-:         SETENA0:1;      CLRENA0:0SETENA0:80000CLRENA0:80000process4:INPUT-:         SETENA0:1;      CLRENA0:1SETENA0:0CLRENA0:0switch the case:************************process5:INPUT-:         CLRENA0:0;      SETENA0:0SETENA0:0CLRENA0:0process6:INPUT-:         CLRENA0:0;      SETENA0:1SETENA0:80000CLRENA0:80000process7:INPUT-:         CLRENA0:1;      SETENA0:0SETENA0:0CLRENA0:0process8:INPUT-:         CLRENA0:1;      SETENA0:1SETENA0:80000CLRENA0:80000

The results verify the feedback conjecture. in the program, the Enable and all assignment conditions and replication sequence are taken into account. However, a new problem arises, why do I set the Enable bit to "1" and the Enable bit to "1" at the beginning? In these cases, all the Enable and the Division can be written in a consistent state. Is this helpful? What do you mean? We can only guess that this is for convenience. no matter whether the read is enable bit or enable bit, we can read an interrupt register randomly. If it is 1, it is enable, and if it is 0, it is divisible.

Of course, all this is just speculation based on the phenomenon. I hope that the great god who understands the hardware will give a convincing explanation. I am very grateful.