Special tubes for FPGA debugging

After debugging an FPGA board, it never works properly after power-on.

 

Phenomenon: nstatus indicators are constantly flashing, and the tested LEDs (FPGA gpio) cannot be lit, that is, FPGA is not working properly.

Debugging process:

1. After FPGA is powered on, it immediately sets the nstatus configuration status pin to a low level, releases it after the power-on Reset (por) is completed, and sets it to a high level. As the configuration status output pin, if any error occurs during the configuration process, the nstatus pin will be set to low.

Nstatus flashes continuously (low-level lighting), indicating that FPGA is not configured successfully.

2. to further identify the cause, measure the FPGA conf_done pin. After power-on, it is found that the conf_done pin is always low. Under normal circumstances, this pin is set to a low level during the configuration process. Once the configuration data is correctly received, FPGA enters the initialization cycle and user mode and releases conf_done, it changes to a high level. Therefore, it is further determined that FPGA is not configured successfully.

3. Measurement of FPGA-related configuration pin impedance. It is found that the local impedance of the conf_done pin is about 600 euro, and the vcc_3.3v impedance is about Euro; normally, the peer and peer vcc_3.3v impedance is about 9.88k and 10.85k. After removing the pull-up resistance (10 K), the Earth and the impedance of 3.3v are 634 and 1.74k, and the normal value is about 5.75m.

4. Check whether the internal configuration circuit of FPGA is damaged. Ah, unfortunately, FPGA chip.

 

Appendix: Special tubes of FPGA

1. I/O, asdo

In as mode, it is a dedicated output foot. In PS and JTAG mode, it can be used as an I/O Foot. In as mode, this foot is the foot where CII sends control signals to the serial configuration chip. It is also used to read configuration data from the configuration chip. In as mode, asdo has an internal pull-up resistor, which is always valid. After the configuration is complete, the foot becomes a three-state input foot. The asdo foot is directly connected to the ASDI foot of the configuration chip (5th feet ).

2. I/O, ncso

In as mode, it is a dedicated output foot. In PS and JTAG mode, it can be used as an I/O Foot. in as mode, this foot is the Enable foot that CII sends to the serial configuration chip outside. In as mode, asdo has an internal pull-up resistor, which is always valid. This foot is valid at a low level. Directly connect to the/CS foot of the configuration chip (1st feet ).

3. I/O, crc_error

When the CRC circuit is selected for error detection, this foot is used as the crc_error foot, which is used for I/O if not used by default. However, you must note that this foot does not support open and reverse pole drain. When it is used as a crc_error, the High-level output indicates a CRC verification error (an error occurred during the configuration of each session of the SRAM ). CRC circuit support can be added in setting. This script is generally used in combination with the nconfig script. If an error occurs during the configuration process, reconfigure the configuration.

4. I/O, clkusr

When the Enable User-supplled start-up clock (clkusr) option is enabled in the software, this foot can only be used as the initialization clock input foot provided by the user. After all the configuration data has been received, the conf_done script changes to a high level. The CII device also needs 299 clock cycles to initialize registers, I/O, and other States. FPGA has two methods, one is an internal crystal oscillator (10 MHz), and the other is the clock received from clkusr (up to 100 MHz ). This feature can be used in special applications that require FPGA synchronization.

5. I/O, vref

It is used to provide a reference level for some differential standards. If not, it can be used as I/O.

6. data0

Dedicated input foot. In as mode, the configuration process is: Cyclone sets ncso to a low level, and the configuration chip is enabled. Cyclone then uses DCLK and asdo to send operation commands and read addresses to the configuration chip. Configure the chip and send data to cyclone through the data script. The data foot is connected to the data0 foot of cyclone. After receiving all the configuration data, cyclone releases the conf_done foot (that is, it does not force the conf_done foot to be low), and The conf_done foot is open-drain. At this time, because conf_done is connected to a 10 k resistor externally, it will become a high level. At the same time, cyclone stops the DCLK signal. After conf_done becomes a high level (then it is equivalent to an input foot), the initialization starts. So,Conf_done must be connected with a 10 k resistor.To ensure that the initialization process can start correctly. Data0, DCLK, ncso, and asdo have weak pull-up resistance, which is always valid. After the configuration is complete, these feet change to three input states, and the internal weak pull-up resistance sets the level to high. In as mode, data0 is connected to the data (2nd feet) configured on the chip ).

7. DCLK

In PS mode, it is input, and in as mode, it is output. In PS mode, DCLK is a clock input foot, which is the clock that an external device sends configuration data to FPGA. Data is written on the rising edge of the DCLK. In the as mode, the DCLK foot is a clock output foot that provides a configuration clock. Directly connect to the DCLK foot of the configuration chip (6th feet ). Regardless of the configuration mode, after the configuration is complete, the script will change to three States. If the external side is a configuration device, the configuration device sets the DCLK foot to a low level. If you are using a master chip, you can set the DCLK to a high level or you can set the DCLK to a low level. After the configuration is complete, triggering this script does not affect the configured FPGA. This foot carries the input buffer and supports the Lag Function of the Schmidt trigger.

8. nce

Dedicated input foot. This foot is a low-level effective chip selection enabling signal. The NCE foot is the configured enable foot. In configuration, initialization, and user mode, the NCE script must be low. During the configuration of multiple devices, the NCE foot of the first device should be low, and its nceo should connect to the NCE foot of the next device to form a chain. In the JTAG programming mode, the NCE script must be kept low. This foot carries the input buffer and supports the Lag Function of the Schmidt trigger.

9. nconfig

Dedicated input pin. This pin is a configuration control input pin. If this foot is set to low in user mode, FPGA will lose its configuration data, enter a reset state, and set all the I/O feet to three States. Nconfig will initiate the reconfiguration process from low-level jump to high-level. If the configuration scheme uses an enhanced configuration device or epc2, you can directly connect the nconfig foot to the VCC or to the ninit_conf foot of the configuration chip. This foot carries the input buffer and supports the Lag Function of the Schmidt trigger. In user mode, the nconfig signal is used to initialize reconfiguration. When the nconfig script is set to low, the initialization process starts. When the nconfig foot is set to low, the CII is reset and enters the reset state. The nstatus and conf_done feet are set to low, and all the I/O feet enter three states. The nconfig signal must be at least 2us. When nconfig returns to the high status, nstatus is released again. Reconfiguration begins. In the actual application process, the nconfig foot can be connected to a 10 k pull-up resistor to 3.3 V.

10. dev_oe

I/O foot or global I/O enable foot. You can enable the dev_oe option (enable device-wideoutput enable) in the Quartus II software. If this feature is enabled, this script can be used as a global I/O enabling script, the function of this foot is that if it is set to low, all I/O enters three states.

11. init_done

An I/O foot or an output foot with an open drain path. When this foot is enabled, the jump from low to high indicates that the FPGA has entered the user mode. If the init_done output foot is enabled, it cannot be used as user I/O after the configuration is complete. You can enable the Enable init_done output option to enable this script in QuartusII.

12. nceo

I/O foot or output foot. After the configuration is complete, the foot outputs a low level. During the configuration of multiple devices, this pin is connected to the NCE pin of the next device. At this time, it also needs to pull a 10 k resistor to the vccio. During the configuration of multiple devices, the nceo of the last device can be left blank. If you want to use this script as an available I/O, you need to set it in the software. In addition, even if I/O is performed, it must be completed after the configuration is complete.

13. nstatus

This is a dedicated configuration status foot. Two-way foot, when it is an output foot, is exposed. After power-on, FPGA immediately sets the nstatus foot to a low level, releases it after power-on Reset (por) is completed, and sets it to a high level. If any error occurs during configuration, the nstatus script is set to low. When a STATUS input foot is configured or initialized, the external control chip can lower the foot, and FPGA will enter the wrong state. This foot cannot be used as a normal I/O Foot. The nstatus foot must have a resistance of 10 KB.

14. conf_done

This is a dedicated configuration status foot. Two-way foot, when it is an output foot, is exposed. When it is used as a status output foot, it is set to low level before and during configuration. Once the configuration data is received and there are no errors, conf_done will be released at the beginning of the initialization cycle. When it is used as a status input foot, you need to set it to a high level after all data is received. Then the device starts initialization and enters the user mode. It cannot be used as a common I/O. The outer part of the foot must also be connected with a resistance of 10 KB.

15. msel [1:0]

These feet need to be connected to zero or power, indicating high or low. 00 indicates the as mode, 10 indicates the PS mode, and 01 indicates the fast as mode. if the JTAG mode is used, 00 is connected. The JTAG mode has nothing to do with msel. That is, JTAG mode is used. msel is ignored, but it cannot be left blank, therefore, we recommend that you connect it to the local device.

16 dev_clrn

I/O or global zero input. In quartuⅱ, if enable device-wide reset (dev_clrn) is selected. This is the global zeroth end. When this pin is set to low, all registers are cleared. This script does not affect the JTAG boundary scan or programming operations.