Spsr and CPSR

Original article: http://blog.chinaunix.net/uid-28458801-id-3487199.html

CPSR: Current Program Status Register, which is accessed in any processor mode. It contains the condition flag bit, the interrupt prohibition bit, the current processor mode mark, and some other control and status bit.
CPSR is used to store condition codes during user-level programming.

Spsr:The program state storage register (saved Program Status Register). Each processor mode has a State register spsr, which is used to save the state of CPSR, this allows you to restore the working status when an exception is returned. When a specific exception interrupt occurs, this register is used to store the content of the current program status register. You can use spsr to restore CPSR when an exception is terminated. Because the user mode and system mode are not the exception interrupt mode, there is no spsr. When users access spsr in user mode or system mode, unpredictable consequences will occur.

The CPSR format is as follows. The format of spsr is the same as that of CPSR.
31 30 29 28 27 26 7 6 5 4 3 2 1 0
N z C v q DNM (Raz) I f t M4 m3 m2 M1 M0

* ** Condition flag ***
N-- Set the base value to the bit [31] value of the current command operation result. For two signed integer operations, n = 1 indicates that the calculation result is negative, and n = 0 indicates that the result is positive or zero.

Z-- Z = 1 indicates that the calculation result is zero; Z = 0 indicates that the calculation result is not zero. For CMP commands, Z = 1 indicates that the two numbers for comparison are of the same size.

C-- The following describes how to set C in four cases:
In addition commands (including comparison command CMP), when the result produces carry, c = 1 indicates that the unsigned operation overflows. In other cases, c = 0.
In the subtraction command (including the subtraction command CMP), if the operation is misaligned, c = 0 indicates that the number of unsigned operations overflows. In other cases, c = 1.
For non-addition and subtraction commands that contain the shift operation, C contains the value of the last overflow bit. For other non-addition or subtraction operation commands, the C-bit value is usually not affected.

V-- For addition and subtraction operation commands, when the operands and operation results are binary complement numbers, V = 1 indicates that the symbols are overflow. Generally, other commands do not affect the V bit.

***Q ID***
In the eseries processor of arm V5, the bit [27] of CPSR is called the Q flag, which is mainly used to indicate whether the enhanced DSP command has exceeded. The bit [27] bits of the same spsr are also called Q flags, which are used to save and restore the Q flags in CPSR when an exception is interrupted.
In earlier versions of arm V5 and non-E series Processors of arm V5, Q flag is not defined.

* ** Control bit in CPSR ***
CPSR's low octal I, F, T, and m [] are collectively referred to as control spaces. These bits change when an exception is interrupted. In privileged processor mode, software can modify these control bits.

**Interrupt prohibition bit I, F: IRQ interruption is disabled when I = 1, and FIQ interruption is disabled when F = 1.

**T control bit: The t control bit is used to control the command execution status, indicating whether the command is an arm command or a thumb command. For arm V4 with a later version of the T series ARM processor, the meaning of the t control bit is as follows:
T = 0 indicates executing the arm command
T = 1 indicates executing the thumb command
For arm V5 and later non-T series Processors, the meaning of the t control bit is as follows:
T = 0 indicates executing the arm command
T = 1 indicates that the next execution of the command is forced to generate an undetermined command interrupt.

* ** M control bit ***
The m control bit control processor mode has the following meanings:

M [4: 0] processor ModeAccessible registers
Ob10000 user PC, R14 ~ R0, CPSR
0b10001 fiq pc, R14_FIQ-R8_FIQ, R7 ~ R0, CPSR, spsr_fiq
0b10010 irq pc, R14_IRQ-R13_IRQ, R12 ~ R0, CPSR, spsr_irq
0b10011 supervisor PC, R14_SVC-R13_SVC, R12 ~ R0, CPSR, spsr_svc
0b10111 abort PC, R14_ABT-R13_ABT, R12 ~ R0, CPSR, spsr_abt
0b11011 undefineed PC, R14_UND-R8_UND, R12 ~ R0, CPSR, spsr_und
0b11111 system PC, R14-R0, CPSR (arm V4 and later)

* ** Other bits in CPSR ***
These bits are used for future expansion. Do not operate these bits in the application software.

(CPSR, spsr) Access command
ARM microprocessor Supports Program Status Register Access commands, which are used to transmit data between Program Status Register and general register. Program Status Register Access Commands include the following two:
-Mrs: data transfer instruction from the Program Status Register to the General Register
-MSR: Data Transfer Instruction from General registers to program status registers

1. Mrs command
The format of the Mrs command is: common register of Mrs {condition}, Program Status Register (CPSR or spsr)
The Mrs command is used to transmit the content of the Program Status Register to the General Register. This command is generally used in the following situations:
-When you need to change the content of the Program Status Register, you can use Mrs to read the content of the Program Status Register into the General Register, and then write it back to the Program Status Register after modification.
-During exception handling or process switching, you need to save the value of the Program Status Register. You can use this command to read the value of the Program Status Register and then save it.
Command example:
Mrs r0, CPSR; transmits CPSR content to R0
Transmit the spsr content to R0.

2. MSR commands
MSR Command Format: MSR {condition} Program Status Register (CPSR or spsr) _ <field>, operand
The MSR command is used to transmit the content of the operand to a specific domain of the Program Status Register. The operands can be General registers or immediate numbers. <Domain> it is used to set the bit to be operated in the Program Status Register. The 32-bit program status register can be divided into four fields:
Bit [31: 24] is the condition flag bit field, expressed in F;
Bit [] is the State bit domain, represented by S;
The bitwise [] is an extended bitwise domain, represented by X;
The digit [] is the control bit field, expressed in C;
This command is usually used to recover or change the content of the Program Status Register. during use, it is generally necessary to specify the domain to be operated in the MSR command.
Command example:
Msr cpsr, R0; transmits R0 content to CPSR
MSR spsr, R0; transmits R0 content to spsr
MSR cpsr_c, R0; transmits R0 content to spsr, but only modifies the control bit domain in CPSR

1. Status Registers are transferred to general register commands.
Function: transfers the Status Register content to a common register.

Format:
Mrs {<condition code >}rd, CPSR} spsr
Where:
Rd target register. RD does not allow R15.
R = 0 transfers the content in CPSR to the destination register.
R = 1 transfer the content in spsr to the destination register.

Note:
Mrs and MSR are used in combination as part of the read-Modify-write sequence for updating dsrs. For example, change the processor or clear the flag Q. Note: When the processor is in user or system mode, it cannot attempt to access the spsr command without affecting the condition code mark.
Example:
Mrs r0, crsr; transmits content in CPSR to R0
Mrs R3, spsr; transmits the content in spsr to r3

2. Transfer commands from General registers to status registers
Function: transfers the content of the General Register to the Status Register.

Format:
MSR {<condition code> cpsr_f | spsr_f, <# ommed_8r>
MSR {<condition code> CPSR _ <field> | spsr _ <field>, RM
Where:
<Field> fields can be one or more of the following:
C: control domain shielding fields (0th-7th bits in the "SRS" field );
X: extended domain shielding field (8th-15th bits in the "SRS" field );
S: The Status domain shielding field (16th-32nd bits in the SRS );
F: indicates the domain blocking field (24th-31st bits in the SRs ).
The expression of the immed_8r value numeric constant. The constant must correspond to an 8-Bit Bitmap. This bitmap shifts an even number cyclically in 32-bit characters.
Rm source register.

Note:
The same as the previous command (MRS ).
Example 1: set N, Z, C, and V.
MSR cpsr_f, # & f0000000; valid only for high positions. Other values must be 0.
Example 2:
Only set the C flag, and retain the N, Z, and V signs.
Mrs r0, CPSR; transmits content in CPSR to R0
ORR r0, R0, # & 1f; Set 29th bits of R0
MSR cpsr_c, R0; then transmits the content in R0 to CPSR

Spsr and CPSR