Stm32 Objective C

From: http://blog.csdn.net/huangtonggao/article/details/6441876

Stm32 (Cortex-M3) has two priority concepts-preemptible priority and response priority, some people call the response priority as 'subpriority 'or 'subpriority ', each interrupt source must be assigned these two priorities.

An interrupt with a high preemptible priority can be responded to during interrupt processing with a low preemptible priority, that is, interruption nesting, or an interrupt with a higher preemptible priority can be nested with an interrupt with a lower preemptible priority.

When the preemptible priorities of the two interrupt sources are the same, there is no nested relationship between the two interrupts. When one interrupt arrives, if another interrupt is being processed, the resulting interruption will not be processed until the previous interruption is completed. If the two interrupts arrive at the same time, the Interrupt Controller determines which one to process based on their response priority. If both their preemptible priority and response priority are equal, then, they decide which one to process first based on their ranking order in the interrupt table.

Since each interrupt source needs to be specified with these two priorities, the corresponding register bit is required to record the priority of each interrupt; in the Cortex-M3, 8 bits are defined to set the priority of the interrupt source, which can have 8 allocation methods, as shown below:

All eight bits are used to specify the response priority.
The top 1 bits are used to specify the preemptible priority, and the lowest 7 bits are used to specify the response priority.
The maximum two bits are used to specify the preemptible priority, and the lowest six bits are used to specify the response priority.
The maximum three bits are used to specify the preemptible priority, and the minimum five bits are used to specify the response priority.
The maximum 4 bits are used to specify the preemptible priority, and the minimum 4 bits are used to specify the response priority.
The maximum 5 bits are used to specify the preemptible priority, and the minimum 3 bits are used to specify the response priority.
The highest 6 bits are used to specify the preemptible priority, and the lowest 2 bits are used to specify the response priority.
The maximum 7 bits are used to specify the preemptible priority, and the lowest 1 bits are used to specify the response priority.

This is the concept of priority group.

The Cortex-M3 allows the use of a smaller register bit to specify the priority of the interrupt source when there is a smaller interrupt source, so the stm32 reduces the number of register bits that specify the interrupt priority to four bits, the four register bit grouping methods are as follows:

Group 0th: all four bits are used to specify the response priority.
Group 1st: the maximum value of 1 is used to specify the preemptible priority, and the minimum value of 3 is used to specify the response priority.
Group 2nd: the highest two bits are used to specify the preemptible priority, and the lowest two bits are used to specify the response priority.
Group 3rd: The maximum three bits are used to specify the preemptible priority, and the lowest one is used to specify the response priority.
Group 4th: all four bits are used to specify the preemptible priority.

You can choose which priority grouping mode to use by calling the nvic_prioritygroupconfig () function in the Firmware Library of stm32. The function has the following five parameters:

Nvic_prioritygroup_0 => select 0th groups
Nvic_prioritygroup_1 => select 1st groups
Nvic_prioritygroup_2 => select 2nd groups
Nvic_prioritygroup_3 => select 3rd groups
Nvic_prioritygroup_4 => select 4th groups

The next step is to specify the priority of the interrupt source. The following is a simple example to illustrate how to specify the preemptible priority and response priority of the interrupt source:

// Select a priority group of 1st
Nvic_prioritygroupconfig (nvic_prioritygroup_1 );

// Enable exti0 interruption
Nvic_initstructure.nvic_irqchannel = exti0_irqchannel;
Nvic_initstructure.nvic_irqchannelpreemptionpriority = 1; // specify preemptible Priority Level 1

Nvic_initstructure.nvic_irqchannelsubpriority = 0; // specify the response priority level 0
Nvic_initstructure.nvic_irqchannelcmd = Enable;
Nvic_init (& nvic_initstructure );

// Enable exti9_5 interruption
Nvic_initstructure.nvic_irqchannel = exti9_5_irqchannel;
Nvic_initstructure.nvic_irqchannelpreemptionpriority = 0; // specify the preemptible priority level 0
Nvic_initstructure.nvic_irqchannelsubpriority = 1; // specify response Priority Level 1
Nvic_initstructure.nvic_irqchannelcmd = Enable;
Nvic_init (& nvic_initstructure );

Note the following:

1) if the specified preemptible priority level or response priority level exceeds the range specified by the selected priority group, unexpected results may be obtained;

2) There is no nested relationship between interrupt sources with the same preemptible priority level;

3) If an interrupt source is specified as a preemptible priority level, and no other interrupt source is in the same preemptible priority level, you can specify any effective response priority for the interrupt source.

 

 

 

 

The following is an understanding of cool people:

 

 

Finally, I understood it.

Stm32 has an interrupt source for the settable of 43 channels; AIRC (Application interrupt and reset register) registers have 4 bits for the specified priority. The four bits are used to assign the preemption priority and sub priority. They are defined in the stm32 Firmware Library as follows:
/* Preemption priority group -------------------------------------------------*/
# Define nvic_prioritygroup_0 (u32) 0x700)/* 0 bits for pre-emption priority
4 bits for subpriority */
# Define nvic_prioritygroup_1 (u32) 0x600)/* 1 bits for pre-emption priority
3 bits for subpriority */
# Define nvic_prioritygroup_2 (u32) 0x500)/* 2 bits for pre-emption priority
2 bits for subpriority */
# Define nvic_prioritygroup_3 (u32) 0x400)/* 3 bits for pre-emption priority
1 bits for subpriority */
# Define nvic_prioritygroup_4 (u32) 0x300)/* 4 bits for pre-emption priority
0 bits for subpriority */

Visualization:

You are God,
43 people have been created, so many people have to be divided into social class and social class;
Because "class" has a heavy part of speech; "class" is neutral,
So preemption priority-> class; each class contains some class, sub priority-> class;

If the score is based on nvic_prioritygroup_4, it is divided into 16 classes (one class is one preemption priority), 0 class; high class people, it can interrupt low-class people who are doing things (nesting). A maximum of one interrupt and 15 levels of nesting can be completed.
For each class (each preemption priority), you can specify the 43 people who enter the class; for a person named exti0_irqchannel, you specify him to Enter Class 8, then
Nvic_initstructure.nvic_irqchannel = exti0_irqchannel;
Nvic_initstructure.nvic_irqchannelpreemptionpriority = 8; // specify the preemptible priority level. The value ranges from 0 to 15.

In addition, when a person is working in the same class, another person cannot interrupt him; (there is no nested relationship between the source of the same preemption priority level)
Also, if the two of them want to do things at the same time, because there is no class, they will sort the physical order in the vector table and let the top people do it;

Another person, spigot irqchannel, is set as follows:
Nvic_initstructure.nvic_irqchannel = spi1_irqchannel;
Nvic_initstructure.nvic_irqchannelpreemptionpriority = 0; // specify the preemptible priority level. The value ranges from 0 to 15.

Spigot irqchannel has a high class, And exti0_irqchannel can interrupt (nested) when doing things ).

If the score is based on nvic_prioritygroup_3, it is divided into eight classes (one class is one preemption priority), each class has two classes (sub priority); high class people, it can interrupt low-class people who are doing things (nesting). A maximum of one interrupt and seven levels of nesting can be completed.

For each class (each preemption priority), you can specify the 43 people who enter the class; for a person named exti0_irqchannel, you specify him to Enter Class 3, then:
Nvic_initstructure.nvic_irqchannel = exti0_irqchannel;
Nvic_initstructure.nvic_irqchannelpreemptionpriority = 3; // specify the preemptible priority level. The value ranges from 0 to 7.
You also need to specify his class:
Nvic_initstructure.nvic_irqchannelsubpriority = 0; // specify the response priority level. The value ranges from 0 to 1.

Another person is exti9_5_irqchannel. His Class and Class are set as follows:
Nvic_initstructure.nvic_irqchannel = exti9_5_irqchannel;
Nvic_initstructure.nvic_irqchannelpreemptionpriority = 3; // specify the preemptible priority level. The value ranges from 0 to 7.
Nvic_initstructure.nvic_irqchannelsubpriority = 1; // specify the response priority.

The two are brothers of the same class. When a person is working, the other person cannot interrupt him. (There is no nested relationship between the source of the same preemption priority level)
If both of them want to do things at the same time, the former has a higher class, so the former has a higher priority.

Another person is usartjavasirqchannel. His Class and Class are set as follows:
Nvic_initstructure.nvic_irqchannel = usart?irqchannel;
Nvic_initstructure.nvic_irqchannelpreemptionpriority = 2; // specify the preemptible priority level. The value ranges from 0 to 7.
Nvic_initstructure.nvic_irqchannelsubpriority = 1; // specify the response priority.

Usartjavasirqchannel has the highest priority. When two people do things, they can interrupt (nesting ).

And so on.

 

Conclusion:

1) The smaller the preemption priority, the higher the priority. Interruptions with the same preemption priority cannot be nested;

2) When n interruptions with the same preemptible priority occur, the interruptions with a smaller response priority are executed first (not nested). If the response priority is the same, then, it is determined based on the position of the corresponding vector table of each interrupt, And the interrupt first responds to the forward of the vector table.