STM32 's Fsmc__stm32

FSMC LCD Color Learning

 

Color Screen Driver Here is the main use of the 8080-port interface, color screen here with the controller and without the controller, 80 and the mouth has the following signal lines:

CS: Chip selection signal

WR: Write Data

RD: Reading data

RST: Resetting

RS: Command/Data flag (0: Read-write command 1: read-write data)

 

80-Port Read and write process:

①: Set RS According to the type of write or read data to choose

(RS: Command/Data flag (0: Read-write command 1: read-write data)

②: Pull down the signal of the plate selection

③: Set RD/WR to low depending on whether the data is read or written, and then:

On the ascent of RD, the data is latched to the data line (d[7:0]);

The ascent along the WR, which makes the data written;

Figure 80 with the mouth writing data

Figure 80 with the mouth reading data

STM32 's FSMC

FSMC, a flexible static storage controller capable of connecting to synchronous or asynchronous memory and 16-bit PC memory cards, STM32F4 's FSMC interface supports memory including SRAM, NAND Flash, NOR Flash, and Psram.

all external memory shares addresses, data, and control signals, but has its own slice-and-choose signal. FSMC can only access one external device at a time.

 

main functions of STM32 FSMC: (see Manual for details)

Support for burst mode access to synchronous devices (NOR Flash and Psram)

8 or 16-bit wide data bus

Separate slice control for each storage area

Each storage area can be configured independently

Time series can be programmed to support a variety of devices

FSMC contains four main modules:

AHB interface (including FSMC configuration registers)

NOR Flash/psram Controller

NAND FLASH/PC Card Controller

External Device Interface

Here we introduce why the TFTLCD as an SRAM device: First we understand the next external SRAM connection, external SRAM control generally include: Address line (such as A0~A18), data lines (such as d0~d15), write Signal (WE), read signal (O E), the chip Select Signal (CS), if the SRAM supports byte control, then there is also a ub/lb signal. And the TFTLCD signal includes: RS, d0~d15, WR, RD, CS, RST and BL, and so on, which really need to operate the LCD when the only: RS, d0~d15, WR, RD and CS. Its operation sequence and SRAM control exactly the same, the only difference is that TFTLCD has RS signal, but no address signal. TFTLCD through the RS signal to determine the transmission of data is data or command, essentially can be understood as an address signal, such as we put RS in the A0 above, then when the FSMC controller to write address 0, will make A0 into 0, for TFTLCD, is to write commands. and FSMC write address 1, A0 will become 1, for TFTLCD, is to write data. In this way, the data and commands are separated, they are actually the corresponding SRAM operation of two consecutive addresses.

External Device Address mapping

from the FSMC point of view, the external memory is divided into 4 fixed-size storage areas, each area of the size of 256MB, the following figure:

Storage area 1 connects up to 4 NOR Flash or psram memory devices. This storage area is divided into 4

Nor/psram area, with 4 special slice signal.

Storage areas 2 and 3 are used to connect NAND Flash devices (one device per storage area)

Storage area 4 for connecting PC card devices

from the above figure that FSMC total 1GB space management, with 4 storage blocks (Bank), where we discuss the storage block 1 (BANK1), Bank1 divided into 4 areas, each 64M byte space, each zone has a separate register for the attached storage to configure. The BANK1 256M byte space is addressed by 28 address lines (haddr[27:0]).

here haddr is the internal AHB address bus select、read, where haddr[25:0] comes from the external memory address fsmc_a[25:0, and haddr[26:27] addresses 4 areas, as shown below:

 

harrd[25:0] contains the external memory address, because the HARRD is a byte address, and the memory is addressed by word, so depending on the width of the memory data, the actual address sent to the memory will be different, as shown in the following figure:

 

 

 

 

when the BANK1 is connected to a 16-bit width memory: haddr[25:1]-->fsmc[24:0].

when the BANK1 is connected to a 8-bit width memory: haddr[25:0]-->fsmc[25:0].

regardless of external 8-bit/16-bit wide device, fsmc_a[0] is always connected to the external device address a[0].

 

TFTLCD is using 16-bit data width, so haddr[0] is not used, only haddr[25:1] is effective, the corresponding relationship into: haddr[25:1]-->fsmc[24:0, the equivalent of a move to the right, please pay special attention here. In addition, the setting of haddr[27:26] is not necessary for us to intervene, for example: When you choose to use the third area of Bank1, that is, use FSMC_NE3 to connect the external devices, that is, corresponding to the haddr[27:26]=10, we have to do is to configure the corresponding section 3 register group , to adapt to external equipment.

Stm32f4 's FSMC each bank configuration register as a table

 

for nor flash controllers, it is mainly through FSMC_BCRX, Fsmc_btrx and Fsmc_bwtrx register settings (where x=1~4, corresponding to 4 extents). With these 3 registers, you can set the timing parameters of FSMC access to external memory and widen the speed range of the external memory that can be selected. FSMC's nor flash controller supports both synchronous and asynchronous bursts of access. When the synchronous burst access mode is selected, the FSMC hclk (System clock) is divided and sent to the external memory as the synchronous clock signal fsmc_clk. There are 2 time parameters for the setting you want:

 

the frequency-dividing coefficient (clkdiv) of ①:HCLK and FSMC_CLK can be 2~16;

②: Wait delay (Datlat) required to obtain 1th data in synchronous burst access.

for asynchronous burst access, FSMC mainly sets 3 time parameters: Address Establishment time (ADDSET), Data Establishment time (Datset), and address retention time (ADDHLD).

FSMC combines the signal characteristics of Sram/rom, Psram and NOR Flash products, and defines 4 different asynchronous timing models. When choosing a different time series model, you need to set the

the same timing parameters, such as Tables

 

 

                                                                        

in actual expansion, the time series model is determined according to the characteristics of the selected memory, and the calculation relation between each time parameter and memory reading/writing period parameter index is determined, and the parameters of the FSMC are calculated by using the calculation relation and the parameter index given in the data Manual of the memory chip. Thus, the time parameter register is configured reasonably.

We use the asynchronous mode A (Modea) method to control the TFTLCD, and the read operation sequence of pattern A is shown in the figure

Pattern A read operation sequence diagram

Mode A supports independent read and write timing control, which is very useful for us to drive TFTLCD,

because when TFTLCD is reading, generally relatively slow, and in writing can be faster, if read and write with the same timing, then only to read the timing as the benchmark, which causes the writing speed to slow, or in the reading data, reconfigure FSMC delay, in the reading operation is completed, And then configure the back-write timing, although it will not reduce the speed of writing, but frequently configured, more cumbersome. And if there is an independent read and write timing control, then we just initialize the time configuration, then no longer configure, both to meet the speed requirements, and do not need to change the configuration frequently.

 

pattern A writes the sequence as shown in the figure:

pattern A write operation sequence

The AddSet and dataset in the figure are set by different registers.

Sram/nor Flash Chip Selector control register: FSMC_BCRX (x=1~4), the register each bit as shown:

 

Extmod: Extended mode to enable bit, that is, whether or not to allow reading and writing different timing

WREN: Write to make the energy bit. We need to write data to TFTLCD, so this bit must be set to 1.

mwid[1:0]: Memory data bus width. 00, representing 8-bit data mode; 01 for 16-bit

data patterns, 10 and 11 retention. Our TFTLCD is a 16-bit data cable,

so set wmid[1:0]=01.

mtyp[1:0]: Memory type. 00 means SRAM, ROM, 01 means psram;

represents NOR flash;11 retention. As mentioned earlier, we regard TFTLCD as

SRAM used, so need to set mtyp[1:0]=00.

Mbken: Storage blocks enable bits. This is easy to understand and we need to use this block to control TFTLCD,

of course we have to make this memory block.

 

Sram/nor Flash memory tablet selection sequence Register: Fsmc_btrx (x=1~4)

 

This register contains control information for each memory block and can be used for SRAM, ROM, and nor flash memory. If the EXTMOD bit is set in the FSMC_BCRX register, there are two sequential registers corresponding to the read (this register) and write operations (Fsmc_bwtrx registers) respectively. Because we require read and write separate timing control, so Extmod is enabled, that is, this register is a read-operation sequence register, control the reading operation of the relevant time series. The settings we want to use in this chapter are:

Accmod, Datast and AddSet these three settings.

accmod[1:0]: access mode. 00 means access mode A; 01 means access mode B;

means access mode c;11 represents access mode D, we use pattern A in this chapter,

so set to 00.

datast[7:0]: Data retention time. 0 is set for retention, and other settings represent holding time as:

datast a hclk clock cycle with a maximum of 255 hclk cycles.

For ILI9341, it is the RD low level duration, generally

355ns. and a hclk clock cycle is around 6ns (1/168mhz),

to be compatible with other screens, we set the Datast to 60, or 60.

HCLK Cycle, the time is about 360ns.

addset[3:0]: address establishment time. Its establishment time is: AddSet a hclk cycle,

the maximum is 15 hclk cycles. For ILI9341, this is equivalent to RD.

high-level duration, 90ns, we set AddSet,

namely 15*6=90ns.

 

Sram/nor Flash Sequence Register: Fsmc_bwtrx (x=1~4), which registers each

bit description as shown in figure

 

This register is used as a write sequence control register, and we need to use the same settings: Accmod, Datast and AddSet. These three sets of methods are identical to the Fsmc_btrx, but here corresponds to the write operation of the timing, accmod settings and Fsmc_btrx exactly the same, the same choice mode A, and Datast and addset corresponding to the low and high level duration, for the ILI9341 , these two times only need 15ns is enough, much faster than read operation. So here we set the Datast to 2, that is, 3 hclk cycles, and the time is about 18ns. The AddSet is then set to 3, or 3 HCLK cycles, with a time of 18ns. At this point, our FSMC introduction to STM32F4 is about the same, through the above two sections, we can start to write the LCD driver code. However, here also to do the popular science, in the MDK register definition, and did not define FSMC_BCRX, Fsmc_btrx, Fsmc_bwtrx, such as the individual registers, but they have some combination.

Fsmc_bcrx and Fsmc_btrx, grouped into btcr[8] register groups, their corresponding relationships are as follows:

btcr[0] corresponds to fsmc_bcr1,btcr[1] corresponds to FSMC_BTR1

btcr[2] corresponds to fsmc_bcr2,btcr[3] corresponds to FSMC_BTR2

btcr[4] corresponds to fsmc_bcr3,btcr[5] corresponds to FSMC_BTR3

btcr[6] corresponds to fsmc_bcr4,btcr[7] corresponds to FSMC_BTR4

Fsmc_bwtrx are grouped into bwtr[7], and their corresponding relationships are as follows:

Bwtr[0] corresponds to the fsmc_bwtr1,bwtr[2] corresponding to the FSMC_BWTR2,

Bwtr[4] corresponds to the fsmc_bwtr3,bwtr[6] corresponding to the FSMC_BWTR4,

BWTR[1], bwtr[3] and bwtr[5] reserved, no use