Synopsys VCS Learning Notes (i)

1, VCs commonly used compile command:
  VCs source_files [source_or_object_files] Options
e.g VCs TOP.V toil.v-ri +v2k

Details of Options:

-I: Compiles for interactive use

+v2k:enables New language features in the proposed IEEE 1364-2001 standard. See "Implemented IEEE STD 1364-2001 Language constructs" on page 2-23.

- R after compilation, run simulation executable

-ri After compilation, run simulation under Xvcs

-sverilog
Enables the use of the Verilog language extensions in the Accellera
SystemVerilog specification.

-debug
Enables the use of UCLI commands and DVE.

-debug_all
Enables the use of UCLI and DVE. Also enables line stepping.

-doc

Starts browser to display the HTML files for the VCS/VCSI documentation.

-VCD <filename>
Sets the output VCD file name to the specified file.
The default filename is verilog.dump.
A $dumpfile System Task in the Verilog source code would override
This option.

+vcdfile+<filename>
Specifies the VCD file you want to use for post-processing.

-fsdb
To dump an fsdb file

-xman=4:combines All source files to a single file "TOKENS.V"
E.g:vcs ADD4.V top.v-xman=4

-L filename:specifies a file where VCS records compilation messages. If You
Also enter The-r option, vcsrecords messages from both
Compilation and simulation in the same file.

2, Fsdbdumpfile and fsdbdumpvars to dump an fsdb file.
fsdbdumpfile -Specify FSDB file name
-Syntax: $fsdbDumpfile ("FSDB name")
-Function: Save the dump data into a designated file

fsdbdumpvars -Dump specified variable
-Grammar: $fsdbDumpvars; $fsdbDumpvars (Leval,module/var);
-function: Dump the variable you want to observe and store it in the Fsdb file.

$fsdbDumpon, $fsdbDumpfileoff
-function: Turn on/off dump variable function

$fsdbDumpMem, $fsdbDumpMenNow
-Syntax: $fsdbDumpMem, $fsdbDumpMemNow
-Function: Store the memory value to Fsdb file, when the call $fsdbdumpmemnow the memory value will be immediately dump out, and the call $fsdbdumpmem must wait until the end of the time interval to dump out.

Example 1:

 
 
1 initial begin
2   $vcdpluson;
3   $fsdbDumpfile("test.fsdb");
4   $fsdbDumpvars(0,router_test_io);
5 end

Example 2:

 
1 initial begin
2     $vcdpluson;
3     $fsdbDumpfile("test.fsdb");
4     $fsdbDumpvars(0,test);
5 end

Note: Example 1 and Example 2 have all the signal waveforms in the router_test_io and test two modules in the Test.sfdb file.

3. Execute SIMV (binary test file used by VCs generation emulation) file
Command:./SIMV [Run_time_options]

Run_time_options

-s:stops Simulation at time 0

E.g:./simv-s

4. Interactive mode (interactive)
Allows real-time control simulations to be performed, allowing changes to register values or settings during simulation, which can affect simulation results in real time

5. post-processing mode (background processing mode)
The signal of the user-specified selection is first exported to a file, and then the file can be analyzed using Virsim. The file is of type vcd+, and the vcd+ file is a binary format that records information such as the results of VCs simulations, and the history of signal changes.

6, VCs compiler attention issues:
When using VCS compilation, you must first put a document containing ' timescale or macro definitions in front of you, or you will report an error
ERROR-[ITSFM] illegal ' timescale for module
ROUTER_TEST_TOP.SV, 7
Module "Router_test_top" have ' timescale but previous module (s)/package (s) does
Not.
Please refer LRM 1364-2001 section 19.8.

Synopsys VCS Learning Notes (i)