The difference between the RAM of the FPGA

There are two types of RAM, BLock RAM, and distributed RAM on the FPGA.

Block Ram:

1. Bram is a custom RAM resource in FPGA. The location is fixed, for example Bram is a column-by-column distribution, which can result in a longer route delay between user logic and Bram. For the simplest example, in a large-scale FPGA, if you run out of all the Bram, the performance will generally drop, even if the route is not the case, this is the reason. Flexible use of Bram and distributed RAM enables efficient use of FPGA resources for improved performance. If you need more Bram, planning your layout properly can also improve performance, and you can use Planahead for layout planning.

2, the output of Bram need clock

3, large storage applications, the proposed use of Bram; sporadic small ram, generally using DRAM. But it's just a general rule.

Distributed Ram:

1, DRAM is to use logical units to spell out, will waste the LUT resources.

2, DRAM can be a pure combination of logic, that is, give the address immediately out of the data, you can also add register into the clock of RAM.

When using Xilinx FIFO core, there are two types of RAM to choose from, Block memory and distributed memory. The difference is that the former uses the entire two-port RAM resource in the FPGA, while the latter is piecing together the lookup table Form in the FPGA

Xilinx Spartan3an Series FPGAs: A CLB contains 4 slice, of which two slice on the left can be used for storage, shift register, and logical configuration, called Slicem, and two slice on the right can only be used for logical combinations, called Slicel. Each slice has 2 lut,2 storage units, multiplexers, carry chains, etc. A lut and a storage unit are called a logic cell, so a slice is usually equivalent to 2.25 logic cells.

There are two ways of using block RAM. Law one: Use IP core generator; Law II: Use Verilog or VHDL to write a module.

Suddenly found that I want to achieve is not the RAM, but a single can write one, read more than one register group.

The difference between the RAM of the FPGA