The guiding principle of always language

1, each always has only one @ (event-expression).

2. Always blocks can represent timing logic and combinatorial logic.

3, with the Posedge and Negedge keyword is the timing logic that represents the trigger along, there is no signal combination logic or level-sensitive latch. Or they both say.

4. Each signal assigned in always fast must be defined as a Reg or integer[<msb>:<lsb>] identifier. The reshape variable defaults to 32 bits.

5, always block the combined feedback loop should be avoided, always the assignment in the block must be clear. Otherwise, the designer is required to include a level-sensitive latch in the design to maintain the last value before the assignment. The explanations are as follows:

We don't recommend it, you know, it's easy to make mistakes.

Input a,b,c;

Reg D,e;

[Email protected] (A or B or c)//level-sensitive list is a,b,c

Begin

E=d & A & b;//because there is no d in the level-sensitive list, when D changes, E cannot change immediately, until the a,b,c changes. This is equivalent to the existence of a level-sensitive transparent latch in the staging D data.

D=e|c;

End

6, the value of a signal is assigned to the ' BX, the integrated device to interpret it as an unrelated state, the synthesis of the hardware circuit to do simple.

Excerpt from: Verilog Digital system Design Tutorial (Charlie Xia)

The guiding principle of always language