The reason why the parallel adder delay arises?????? How to solve????

This digest is from the "Verilog Digital system Design Tutorial"

Why delay?????

In implementing algorithms, such as convolution operations and Fourier transforms, we often use parallel adders.

Parallel adder is composed of multi-layer logical structure, which must have logical delay and routing delay.

In the multi-bit operation, there is bound to be a delay severity, especially for 32-bit and 64-bit operations.

In this case, we require that the parallel adder should not be used too often, otherwise the cycle is likely to exceed the delay time, i.e. the beat clock must be greater than the delay of the circuit. This will ensure the correctness of use.

The solution?????

In order to speed up the calculation, we can put multiple register groups in the Combinational logic layer of the operation Circuit to postpone the intermediate result.

This design is a common pipeline (pine-line) approach. Later chapters will be introduced in detail ....

**************************************************************************************************

Made by Qidaiymm, your comment is appreciated.

Email:[email protected]

The reason why the parallel adder delay arises?????? How to solve????