Thoughts on reset of Cortex-M3 System

1. Read the cm3 authoritative guide, pointing out that the aircr value written to the reset is (0x5fa <16) | 0x4, but in this process, it takes some time to run on the kernel, so it may continue to be executed until the reset takes effect. At the same time, it will also respond to external interruptions. Therefore, we set faultmask before execution, all interrupts except NMI are blocked. When the reset value is assigned, the while endless loop is added after execution to avoid executing subsequent programs. That is:

__set_FAULTMASK(1);NVIC_SystemReset();

System reset is recommended!

2. Change the Pc value so that the PC points to the Reset vector again. That is:

void Reset(void){    void (*fp)(void);    fp = (void (*)(void))(* (vu32 *)(0x8000004));    (*fp)(); }

Recommended method: Improvement (loading MSP ):

Typedef void (* pfunction) (void); // define the void resettest (void) {pfunction preset; uint32_t resetpc; resetpc = * (vu32 *) (0x08000004); preset = (pfunction) resetpc; _ set_msp (* (vu32 *) 0x08000000); preset ();}

3. The Pc value is also changed:

void Reset(){    void (*fp)(void);    fp = (void (*)(void))0x8000005; //LSB=1    (*fp)(); }

During the test, the PC jump can be written to 0x08000001. During the simulator process, the PC executes the program one by one and the tracing program does not start executing the program from systeminit, instead of the main address, it points to the initial function in the main function to start execution.

The above LSB is 1, because data is written to the PC, it will cause a program Branch (but LR is not updated ), whether Directly Writing the Pc value or using the branch command (the address after the jump command such as BX), ensure that the value loaded to the PC is an odd number (that is, LSB = 1 ), it indicates that this is executed in the thumb state. If 0 is written, it is regarded as an attempt to transfer to the arm mode. cm3 will generate a fault exception --> hardfault.