Time series logic and combination logic. I'm no longer afraid of you.

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• Time series logic and combination logic. I'm no longer afraid of you.

Time series logic and combination logic. I'm no longer afraid of you.

After learning FPGA for so long, we had to use VHDL. At that time, we didn't have the concept of time series logic and combination logic. Later, we had to use OpenGL. At the beginning, we still didn't understand time series logic and combination logic, when doing things, we find that there are always defects.

Once upon a time, the 4.3 inch LCD encountered a depressing problem. The time sequence logic and the combination logic can be used for the pixel, But I Don't Know What To use. Furthermore, when it's accurate, the two methods have different effects, but I don't understand them ......

Once I asked my EDA teacher, he said: "Time series logic and combination logic are the most difficult part in the design of the hardware description language, many senior engineers have not even figured out this ......"

I'm so depressed ...... Such an answer ......

After debugging VGA these days, the pixels are absolutely accurate. After one attempt, I finally understood the timing logic and combination logic, so I don't have to worry about it in the future ......

In fact, the combination logic is: Always @ (sensitive signal) or always @ *. The combination logic is equivalent to a combination circuit, which is composed of a circuit or a non-gate. The output is related to the current status, it has nothing to do with other input state functions and does not involve signal adjustment and transformation processing (combined logic Competition Risk: as long as the input signal changes at the same time, the combined logic will inevitably generate a glitch );

Time series logic: Always @ (Hop-to-clock) is a time series circuit. Its output is not only related to the current status, but also changes only when the clock is switched, the simplest model is equivalent to the DFF and D triggers.

In the VGA driver design, HS and vs are all time series logic, which is equivalent to hcnt. vcnt just lags behind a clock cycle. xpos and ypos are the combination logic of hcnt and vcnt, synchronize with the clock. In the second module, the RGB value is determined by xpos and ypos. This is a time series logic that just lags behind a clock cycle. Therefore, the HS, VS, and RGB pixels in the first and second stages are synchronized. Of course, the xpos and ypos RGB inputs must be determined as the combination logic, this is because it is related to the current State (the reason has been mentioned in the "time series logic _ lagging behind a pixel" section ).

Many people read books, read books, while (1) {read books}; do not understand the combination logic, time series logic;

Now, as long as you understand the meaning, you can use it freely ......