Time series simulation of Modelsim

Using Modelsim for timing simulation (door-level simulation) can reflect the device latency more realistically, but it also requires the support of the relevant device atom library.
The following is a brief description of the instance with a divider:
1. Create a New Div project in quartuⅱ. Pay attention to the settings of EDA simulator. You can set it when creating a project or set it later,

Select Modelsim for Tool Name, and format for output netlist select start. VO. VHO's VHDL output file). Other files can be output by default.
2. Add and compile the source file. The simulation> Modelsim folder is generated in the current project directory, which stores the files required for the simulation, such. VO (*** output file ),. SDO (delayed files.
3. Open Modelsim and create a div project under the created Modelsim folder path. For comparison, functional simulation and timing simulation are performed respectively.
First, functional simulation. This is relatively simple. directly add the Div. V source file and the div_tb.v test file, compile the file, and run the simulation directly. The result is as follows:

We can see that there is no delay in the input and output, and only functional simulation is performed.
4. Perform time series simulation. At this time, you need to add related pre-compiled libraries and delayed files.
A) Convert the previous Div. remove the V file and add the div. VO file (because Div. vo is Div. v. VO), and then compile the div. vo and div_tb.v.
B) Start simulation settings.
First, add the pre-compiled device library. In this example, cycloneii_atoms is used to locate and add it. (The compilation of this library has been mentioned before and I will not talk about it here ), after completion:

Then, add the SDF latency file, that is, the generated Div. SDO file. Click Add and the following window appears:

Add the SDF file first. Another option is apply to region. Enter u_div here. This option mainly specifies the Object Name of the time series simulation, that is, the DIV name instantiated in testbench (u_div ), OK.
The added result is as follows:

C) after completing the preceding settings, you can start the simulation. Click the div_tb top-level entity to start simulation.

The simulation result is enlarged as follows:

Compared with the previous functional simulation results, we can see that the input and output have a certain delay, measured at 6063 ps, about 6 ns.
Our device selection is ep2c25f672c6, that is, its speed level is C6, that is, the minimum latency can reach 6 NS, so the above timing simulation results are also consistent with this.

This section briefly describes the time series simulation of ModelSim. In fact, it can make the simulation more convenient. For example, it can automatically run the time series simulation (door-level) after the compilation of quartuⅱ, these will be supplemented later.