Timequest Timing Analyzer of us 12

Timequest Timing Analyzer of us 12

1. Enable and design the Quartus II Software

Installation path \ qdesigns \ fir_fliter file. In the processing menu, point to start and click Start Analysis & synthesis.

2. Run timequest Timing Analyzer

In the Tools menu, click timequest Timing Analyzer ,.

 

3. Create a post-map time series network table

1. Click Create timing netlist in the netlist menu. The create timing netlist dialog box is displayed.

2. In input netlist, select post-map.

3. Click OK.

Note: you cannot use the create timing netlist command in the tasks panel to create a post-map time series network table. By default, create timing netlist requires a post-fit database.

Select "post-map" as input netlist and press OK. Timing netlist is created. (If you see "create timing netlist" items, check the hidden color.) (if you see the "Create timing netlist" item, check the green color)

 

5. Specify timing requirements

Two clocks must be defined in the fir_filter design. For the attribute list of each clock, see.

Clock port name	Requirements
CLK	50 MHz of 50/50 duty cycle
Clkx2	60/40 MHz of 100 duty cycle

 

1. In the constraints menu, click Create clock. The createclock dialog box appears.

2. Specify parameters for the 50 MHz clock in Table 2-2. Repeat these steps for a 100 MHz clock.

 

When the third step is executed, the dialog box shown is displayed, and you can set it accordingly.

 

6. Update the time series network table

On the tasks panel, double-click the update timing netlist command.

7. Save the Synopsys Design constraints (SDC) file.

1. On the tasks panel, double-click the write sdc file command. The writesdc file dialog box is displayed.

2. Enter filtref. SDC in the file name column.

 

8. Generate a Time Series Report for the initial time series network table.

On the tasks panel, double-click the report SDC command.

Double-click the report clock command on the task panel to summarize all the clocks.

Double-click the report clock transfer command on the task Panel to verify that all clock-to-clock transmission is effective.

 

The clock transfers report indicates that there is a cross-clock domain between CLK (source clock) and clkx2 (destination clock ).

Path. There are 16 paths in total, with CLK providing the clock for the source node and clkx2 providing the clock for the target node.

In fir_filter design, you do not need to analyze the clock transmission from CLK to clkx2 because they are ignore paths. Connect

In Table 2-13, the program declares that the path from CLK to clkx2 is a pseudo path. After the program is completed, timequest

Timing Analyzer indicates that the clock Transfers Report is outdated.

Generate pseudo Path 1. In the clock Transfers Report, select clk in the from clock column.

2. Right-click and select set False paths between clock domains. This command sets the path between all CLK-driven source registers and target registers driven by clkx2 to a pseudo path.

Update a time series network table.

Save the constraint file to SDC

9. Execute timing-driven Compilation

1. Click Add/Remove files in project in the project menu. Output

The Add/Remove files in project dialog box is displayed.

2. Select. SDC through browsing.

3. Click OK.

In the processing menu, click Start compilation.

10 The fir_filter design must be fully constrained, and all input and output ports must be constrained. Use set input delay and

Set output delay dialog box, or set_input_delay and set_output_delay constraints to specify

Input and Output latency values.

1. In the constraints menu, click set input delay. Set appears

Input delay dialog box.

2. Enter the following content:

Clock name: CLK

Delay value: 2

Targets: [get_ports {d [0] d [1] d [2] d [3] d [4] d [5] d [6] d [7] Newt reset}]

3. In the constraints menu, click set output delay. The setoutput delay dialog box appears.

4. Enter the following content:

Clock name: CLK

Delay value: 1.5

Targets: [get_ports {yn_out [0] yn_out [1] yn_out [2] yn_out [3] yn_out [4] yn_out [5] \ yn_out [6] yn_out [7] yvalid follow}]

Remember to read the new constraints and update the time series network table.

1. On the tasks panel, double-click report timing. Report timing

Dialog box.

2. Enter the following content:

To clock: CLK

To: ACC: inst3 | result *

Report number of paths: 10

3. Use the default settings for the remaining columns.

Double-click report timing.

 

Timequest Timing Analyzer of us 12