Tutorial: Compile u-boot1.1.4 and above to start the development board based on S3C2410

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Tutorial: Compile u-boot1.1.4 and above to start the development board based on S3C2410 -- Linux general technology-Linux programming and kernel information, the following is the details to read. Someone has tried to compile U-BOOT 1.1.4 or above to start the S3C2410/SMDK2410 compatible development board? I recently tried to compile U-BOOT-1.1.4, U-BOOT-1.1.5, U-BOOT-1.1.6 and U-BOOT-2006-06-30-2020, using the Development Board is Chengdu Bo Rui MC2410A. MC2410A is said to be based on S3C2410, but Chengdu borui made some changes on the basis of S3C2410. The basic configuration is ARM920T, 64 mb sdram and 64 mb nand flash, without nor flash. MC2410A can be started with vivi bootloader. however, after I burned the compiled u-boot.bin to the nand flash through the JTAG interface, the power off and then power up without any screen display (I connected the CONSOLE through the serial port ). I tried to modify the u-boot.lds under the u-boot/board/smdk2410/directory, put SECTIONS {...} In the first line ". = 0x ..." Changed to 0x33f80000, 0x33f00000, or 0x00000000. I also tried using head in the vivi/arch/s3c2410/directory. S completely replaces start under u-boot/cpu/arm920t. s, look at the beginning of the "_ start:" assembly code in the u-boot.bin can be recognized by hardware, however, nothing happens (I inserted the Assembly print statement in this assembly code to output debugging information to the serial port, which can be printed normally after being compiled in VIVI ). I have not modified any Makefile or config. mk. I don't know if it is related to Makefile settings. which of the following heroes can help me find out? Thanks first.

Here is the replacement of u-boot/cpu/arm920t/start. S vivi/arch/s3c2410/head. s. in VIVI compilation can be started normally, put in the U-BOOT did not respond.

/*
* Vivi/arch/s3c2410/head. S:
* Initialise hardware
*
* Copyright (C) 2001 MIZI Research, Inc.
*
* This program is free software; you can redistribute it and/or modify
* It under the terms of the GNU General Public License as published
* The Free Software Foundation; either version 2 of the License, or
* (At your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* But without any warranty; without even the implied warranty
* MERCHANTABILITY or fitness for a special PURPOSE. See
* GNU General Public License for more details.
*
* You shoshould have written ed a copy of the GNU General Public License
* Along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*
* Author: Janghoon Lyu
* Date: $ Date: 2003/02/26 10:38:11 $
*
* $ Revision: 1.18 $
*
*
* History:
*
* 2002-05-14: Janghoon Lyu
*-Initial code
*
*/

# Include "linkage-vivi.h"

@ Start of executable code

ENTRY (_ start)
ENTRY (ResetEntryPoint)

@
@ Exception vector table (physical address = 0x00000000)
@

@ 0x00: Reset
BReset

@ 0x04: Undefined instruction exception
UndefEntryPoint:
BHandleUndef

@ 0x08: Software interrupt exception
SWIEntryPoint:
BHandleSWI

@ 0x0c: Prefetch Abort (Instruction Fetch Memory Abort)
PrefetchAbortEnteryPoint:
BHandlePrefetchAbort

@ 0x10: Data Access Memory Abort
DataAbortEntryPoint:
BHandleDataAbort

@ 0x14: Not used
NotUsedEntryPoint:
BHandleNotUsed

@ 0x18: IRQ (Interrupt Request) exception
IRQEntryPoint:
BHandleIRQ

@ 0x1c: FIQ (Fast Interrupt Request) exception
FIQEntryPoint:
BHandleFIQ

@
@ VIVI magics
@

@ 0x20: magic number so we can verify that we only put
. Long 0
@ 0x24:
. Long 0
@ 0x28: where this vivi was linked, so we can put it in memory in the right place
. Long _ start
@ 0x2C: this contains the platform, cpu and machine id
. Long 0x010600C1
@ 0x30: vivi capabilities
. Long 0
@ 0x34:
BSleepRamProc

. Balignl 16, 0 xdeadbeef

_ TEXT_BASE:
. Word0x33f00000

. Globl _ armboot_start
_ Armboot_start:
. Word _ start

/*
* These are defined in the board-specific linker script.
*/
. Globl _ bss_start
_ Bss_start:
. Word 0

. Globl _ bss_end
_ Bss_end:
. Word 0


@
@ Start VIVI head
@
Reset:
/*
* Set the cpu to SVC32 mode
*/
Mrsr0, cpsr
Bicr0, r0, # 0x1f
Orrr0, r0, #0xd3
Msrcpsr, r0

@ Disable watch dog timer
Movr0, #0x53000000
Movr1, #0x0
Strr1, [r0]

@ Disable all interrupts
Movr0, #0x4A000000
Movr1, #0 xffffffff
Strr1, [r0, #0x00000008]
Ldrr1, = 0x3ff
Strr1, [r0, # 0x0000001C]

@ Initialise system clocks
Movr1, # CLK_CTL_BASE
Mvnr2, #0xff000000
Strr2, [r1, # oLOCKTIME]

@
Movr0, #0x4C000000
Movr1, #0x3
Strr1, [r0, #0x00000014]

Mrcp15, 0, r1, c1, c0, 0 @ read ctrl register
Orrr1, r1, #0xc0000000 @ Asynchronous
Mcrp15, 0, r1, c1, c0, 0 @ write ctrl register

@ Now, CPU clock is 200 Mhz
Movr1, # CLK_CTL_BASE
Ldrr2, mpll_200mhz
Strr2, [r1, # oMPLLCON]

Blmemsetup

@ All LED on
Movr1, # GPIO_CTL_BASE
Addr1, r1, # oGPIO_F
Ldrr2, = 0x55aa
Strr2, [r1, # oGPIO_CON]
Movr2, # 0xff
Strr2, [r1, # oGPIO_UP]
Movr2, #0x00
Strr2, [r1, # oGPIO_DAT]

@ Set GPIO for UART
Movr1, # GPIO_CTL_BASE
Addr1, r1, # oGPIO_H
Ldrr2, gpio_con_uart
Strr2, [r1, # oGPIO_CON]
Ldrr2, gpio_up_uart
Strr2, [r1, # oGPIO_UP]
BlInitUART

# Ifdef CONFIG_DEBUG_LL
@ Print current Program Counter
Ldrr1, SerBase
Movr0, # '\ R'
BlPrintChar
Movr0, # '\ N'
BlPrintChar
Movr0 ,#'@'
BlPrintChar
Ldrr0, STR_ OK
Ldrr1, SerBase
BlPrintWord
Movr0, pc
BlPrintHexWord
# Endif

Blcopy_myself

@ Jump to ram
Ldrr1, = on_the_ram
Addpc, r1, #0
Nop
Nop
1: b1b @ infinite loop

On_the_ram:

# Ifdef CONFIG_DEBUG_LL
Ldrr1, SerBase
Ldrr0, STR_STACK
BlPrintWord
Ldrr0, DW_STACK_START
BlPrintHexWord
# Endif

@ Get read to call C functions
Ldrsp, DW_STACK_START @ setup stack pointer
Movfp, #0 @ no previous frame, so fp = 0
Mova2, #0 @ set argv to NULL

Blmain @ call main

Movpc, #0x00000000 @ otherwise, reboot

@
@ End VIVI head
@

/*
* Subroutines
*/

@
@ Wake-up codes
@
WakeupStart:
@ Clear sleep reset bit
Ldrr0, PMST_ADDR
Movr1, #0x10
Strr1, [r0]

@ Release the SDRAM signal protections
Ldrr0, PMCTL1_ADDR
Ldrr1, [r0]
Bicr1, r1, #(1 <19) | (1 <18) | (1 <17 ))
Strr1, [r0]

@ Go...
Ldrr0, PMSR0_ADDR @ read a return address
Ldrr1, [r0]
Movpc, r1
Nop
Nop
1: b1b @ infinite loop

SleepRamProc:
@ SDRAM is in the self-refresh mode */
Ldrr0, REFR_ADDR
Ldrr1, [r0]
Orrr1, r1, #(1 <22)
Strr1, [r0]

@ Wait until SDRAM into self-refresh
Movr1, #16
1: subsr1, r1, #1
Bne1b

@ Set the SDRAM singal protections
Ldrr0, PMCTL1_ADDR
Ldrr1, [r0]
Orrr1, r1, #(1 <19) | (1 <18) | (1 <17 ))
Strr1, [r0]

/* Sleep... Now */
Ldrr0, PMCTL0_ADDR
Ldrr1, [r0]
Orrr1, r1, #(1 <3)
Strr1, [r0]
1: b1b

ENTRY (memsetup)
@ Initialise the static memory

@ Set memory control registers
Movr1, #0x48000000
Adrlr0, mem_1__val
Addr2, r0, #52
1: ldrr3, [r0], #4
Strr3, [r1], #4
Cmpr2, r0
Bne1b

Movpc, lr


@
@ Copy_myself: copy vivi to ram
@
Copy_myself:
Movr10, lr

@ Reset NAND
Movr1, # NAND_CTL_BASE
Ldrr2, = 0xf830 @ initial value
Strr2, [r1, # oNFCONF]
Ldrr2, [r1, # oNFCONF]
Bicr2, r2, #0x800 @ enable chip
Strr2, [r1, # oNFCONF]
Movr2, # 0xff @ RESET command
Strbr2, [r1, # oNFCMD]
Movr3, #0 @ wait
1: addr3, r3, #0x1
Cmpr3, # 0xa
Blt1b
2: ldrr2, [r1, # oNFSTAT] @ wait ready
Tstr2, #0x1
Beq2b
Ldrr2, [r1, # oNFCONF]
Orrr2, r2, #0x800 @ disable chip
Strr2, [r1, # oNFCONF]

@ Get read to call C functions (for nand_read ())
Ldrsp, DW_STACK_START @ setup stack pointer
Movfp, #0 @ no previous frame, so fp = 0

@ Copy vivi to RAM
Ldrr0, = 0x33f00000
Mov r1, #0x0
Movr2, #0x20000
Blnand_read_ll

Tstr0, #0x0
Beqok_nand_read
# Ifdef CONFIG_DEBUG_LL
Bad_nand_read:
Ldrr0, STR_FAIL
Ldrr1, SerBase
BlPrintWord
1: b1b @ infinite loop
# Endif

OK _nand_read:
# Ifdef CONFIG_DEBUG_LL
Ldrr0, STR_ OK
Ldrr1, SerBase
BlPrintWord
# Endif

@ Verify
Movr0, #0
Ldrr1, = 0x33f00000
Movr2, #0x400 @ 4 bytes * 1024 = 4K-bytes
Go_next:
Ldrr3, [r0], #4
Ldrr4, [r1], #4
Teqr3, r4
Bnenotmatch
Subsr2, r2, #4
Beqdone_nand_read
Bnego_next
Notmatch:
# Ifdef CONFIG_DEBUG_LL
Subr0, r0, #4
Ldrr1, SerBase
BlPrintHexWord
Ldrr0, STR_FAIL
Ldrr1, SerBase
BlPrintWord
# Endif
1: b1b
Done_nand_read:

# Ifdef CONFIG_DEBUG_LL
Ldrr0, STR_ OK
Ldrr1, SerBase
BlPrintWord
# Endif

Movpc, r10

@ Clear memory
@ R0: start address
@ R1: length
Mem_clear:
Movr2, #0
Movr3, r2
Movr4, r2
Movr5, r2
Movr6, r2
Movr7, r2
Movr8, r2
Movr9, r2

Clear_loop:
Stmiar0 !, {R2-r9}
Subsr1, r1, # (8*4)
Bneclear_loop

Movpc, lr



@ Initialize UART
@
@ R0 = number of UART port
InitUART:
Ldrr1, SerBase
Movr2, #0x0
Strr2, [r1, # oUFCON]
Strr2, [r1, # oUMCON]
Movr2, #0x3
Strr2, [r1, # oULCON]
Ldrr2, = 0x245
Strr2, [r1, # oUCON]
# Define UART_BRD (50000000/(115200*16)-1)
Movr2, # UART_BRD
Strr2, [r1, # oUBRDIV]

Movr3, #100
Movr2, #0x0
1: subr3, r3, #0x1
Tstr2, r3
Bne1b

Movpc, lr


@
@ Exception handling functions
@
HandleUndef:
# Ifdef CONFIG_DEBUG_LL
Movr12, r14
Ldrr0, STR_UNDEF
Ldrr1, SerBase
BlPrintWord
BlPrintFaultAddr
# Endif
1: b1b @ infinite loop

HandleSWI:
# Ifdef CONFIG_DEBUG_LL
Movr12, r14
Ldrr0, STR_SWI
Ldrr1, SerBase
BlPrintWord
BlPrintFaultAddr
# Endif
1: b1b @ infinite loop

HandlePrefetchAbort:
# Ifdef CONFIG_DEBUG_LL
Movr12, r14
Ldrr0, STR_PREFETCH_ABORT
Ldrr1, SerBase
BlPrintWord
BlPrintFaultAddr
# Endif
1: b1b @ infinite loop

HandleDataAbort:
# Ifdef CONFIG_DEBUG_LL
Movr12, r14
Ldrr0, STR_DATA_ABORT
Ldrr1, SerBase
BlPrintWord
BlPrintFaultAddr
# Endif
1: b1b @ infinite loop

HandleIRQ:
# Ifdef CONFIG_DEBUG_LL
Movr12, r14
Ldrr0, STR_IRQ
Ldrr1, SerBase
BlPrintWord
BlPrintFaultAddr
# Endif
1: b1b @ infinite loop

HandleFIQ:
# Ifdef CONFIG_DEBUG_LL
Movr12, r14
Ldrr0, STR_FIQ
Ldrr1, SerBase
BlPrintWord
BlPrintFaultAddr
# Endif
1: b1b @ infinite loop

HandleNotUsed:
# Ifdef CONFIG_DEBUG_LL
Movr12, r14
Ldrr0, STR_NOT_USED
Ldrr1, SerBase
BlPrintWord
BlPrintFaultAddr
# Endif
1: b1b @ infinite loop


@
@ Low Level Debug
@
# Ifdef CONFIG_DEBUG_LL

@
@ PrintFaultAddr: Print falut address
@
@ R12: contains address of instruction + 4
@
PrintFaultAddr:
Movr0, r12 @ Print address of instruction + 4
Ldrr1, SerBase
BlPrintHexWord
Mrcp15, 0, r0, c6, c0, 0 @ Read fault virtual address
Ldrr1, SerBase
BlPrintHexWord
Movpc, lr

@ PrintHexNibble: prints the least-significant nibble in R0 as
@ Hex digit
@ R0 contains nibble to write as Hex
@ R1 contains base of serial port
@ Writes ro with XXX, modifies r0, r1, r2
@ TODO: write ro with XXX reg to error handling
@ Falls through to PrintChar
PrintHexNibble:
Adrr2, HEX_TO_ASCII_TABLE
Andr0, r0, # 0xF
Ldrr0, [r2, r0] @ convert to ascii
BPrintChar

@ PrintChar: prints the character in R0
@ R0 contains the character
@ R1 contains base of serial port
@ Writes ro with XXX, modifies r0, r1, r2
@ TODO: write ro with XXX reg to error handling
PrintChar:
TXBusy:
Ldrr2, [r1, # oUTRSTAT]
Andr2, r2, # UTRSTAT_TX_EMPTY
Tstr2, # UTRSTAT_TX_EMPTY
BeqTXBusy
Strr0, [r1, # oUTXHL]
Movpc, lr

@ PrintWord: prints the 4 characters in R0
@ R0 contains the binary word
@ R1 contains the base of the serial port
@ Writes ro with XXX, modifies r0, r1, r2
@ TODO: write ro with XXX reg to error handling
PrintWord:
Movr3, r0
Movr4, lr
BlPrintChar

Movr0, r3, LSR #8/* shift word right 8 bits */
BlPrintChar

Movr0, r3, LSR #16/* shift word right 16 bits */
BlPrintChar

Movr0, r3, LSR #24/* shift word right 24 bits */
BlPrintChar

Movr0, # '\ R'
BlPrintChar

Movr0, # '\ N'
BlPrintChar

Movpc, r4

@ PrintHexWord: prints the 4 bytes in R0 as 8 hex ascii characters
@ Followed by a newline
@ R0 contains the binary word
@ R1 contains the base of the serial port
@ Writes ro with XXX, modifies r0, r1, r2
@ TODO: write ro with XXX reg to error handling
PrintHexWord:
Movr4, lr
Movr3, r0
Movr0, r3, LSR #28
BlPrintHexNibble
Movr0, r3, LSR #24
BlPrintHexNibble
Movr0, r3, LSR #20
BlPrintHexNibble
Movr0, r3, LSR #16
BlPrintHexNibble
Movr0, r3, LSR #12
BlPrintHexNibble
Movr0, r3, LSR #8
BlPrintHexNibble
Movr0, r3, LSR #4
BlPrintHexNibble
Movr0, r3
BlPrintHexNibble

Movr0, # '\ R'
BlPrintChar

Movr0, # '\ N'
BlPrintChar

Movpc, r4
# Endif

@
@ Data Area
@
@ Memory configuration values
. Align 4
Mem_1__val:
. Long0x22111110 @ vBWSCON
. Long0x00000700 @ vBANKCON0
. Long0x00000700 @ vBANKCON1
. Long0x00000700 @ vBANKCON2
. Long0x00000700 @ vBANKCON3
. Long0x00000700 @ vBANKCON4
. Long0x00000700 @ vBANKCON5
. Long0x00018005 @ vBANKCON6
. Long0x00018005 @ vBANKCON7
. Long0x008E0459 @ vREFRESH
. Long0xb1 @ vBANKSIZE
. Long0x30 @ vMRSRB6
. Long0x30 @ vMRSRB7

@ Processor clock values
. Align 4
Mpll_200mhz:
. Long0x33f00338
@ In1_values for GPIO
Gpio_con_uart:
. Long0x0016faaa
Gpio_up_uart:
. Long0x000007ff

. Align2
DW_STACK_START:
. Word0x33E64000 + 0x00008000-4

# Ifdef CONFIG_DEBUG_LL
. Align2
HEX_TO_ASCII_TABLE:
. Ascii "0123456789 ABCDEF"
STR_STACK:
. Ascii "STKP"
STR_UNDEF:
. Ascii "UNDF"
STR_SWI:
. Ascii "SWI"
STR_PREFETCH_ABORT:
. Ascii "PABT"
STR_DATA_ABORT:
. Ascii "DABT"
STR_IRQ:
. Ascii "IRQ"
STR_FIQ:
. Ascii "FIQ"
STR_NOT_USED:
. Ascii "NUSD"
. Align 2
STR_ OK:
. Ascii "OK"
STR_FAIL:
. Ascii "FAIL"
STR_CR:
. Ascii "\ r \ n"
# Endif

. Align 4
SerBase:
. Long UART0_CTL_BASE

. Align 4
PMCTL0_ADDR:
. Long 0x4c00000c
PMCTL1_ADDR:
. Long 0x56000080
PMST_ADDR:
. Long 0x56213b4
PMSR0_ADDR:
. Long 0x56213b8
REFR_ADDR:
. Long 0x48000024
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