Us II comes with Simulaiton and Modelsim Simulaiton function simulation

Us II comes with Simulaiton and Modelsim Simulaiton function simulation

VS

Directory

Quartus II comes with Simulaiton and 1

ModelSim Simulaiton function simulation 1

I. Advantages and Disadvantages 1

Step 2

1. simulus II comes with simulation 2

2. Modelsim simulation function simulation 4

I. Advantages and Disadvantages

1) The simulation provided by Quartus II is more suitable for beginners. It is a pure GUI and can be simulated with the mouse. It is very concise and clear. However, compared with relatively large projects, complicated projects, purely manual and rigid settings may be helpless in front of the designers, start ModelSim.

2) compared with the simulation provided by Quartus II, Modelsim simulation can also easily set GUI incentives, but more powerful is the testbench test language, which can be used to simulate and test the logic design. For powerful projects, testing usually takes up most of the time. If you still use the simulation provided by Quartus II, the designers will inevitably suffer. Complicated and powerful at the same time, Modelsim simulation is more suitable for project development, and skilled use of Modelsim will inevitably bring twice the result with half the effort to FPGA development projects.

2. Mutual Simulation step 1. simulus II comes with simulation

1) create a wave_test Project

2) EditCodeAs follows:

/*-------------------------------------------------------------------------

This confidential and proprietary software may be only used as authorized

By a licensing agreement from crazybingo.

(C) Copyright 2012 crazybingo. All Rights Reserved

Filename: led_matrix_display.v

Author: crazybingo

Data: 2012-01-18

Version: 0.1

Description: This file has the module of led_matrix_display top.

Modification history:

Data by version change description

========================================================== ==========================================

12/01/18 crazybingo 0.1 original

--------------------------------------------------------------------------*/

'Timescale 1ns/1ns

Module wave_test

(

// Golobal clock

Input CLK,

Input rst_n,

// Divide clock

Output clk_out,

// Adder Signals

Input [7:0] din1,

Input [7:0] din2,

Output Reg [7:0] dout,

// Self add data

Output Reg [3: 0] addout

);

//-------------------------------------

// Divide clock

Reg [1:0] CNT;

Always @ (posedge CLK or negedge rst_n)

Begin

If (! Rst_n)

CNT <= 2' B0;

Else

CNT <= CNT + 1' B1;

End

Assign clk_out = CNT [1];

//-------------------------------------

// Add din1 with din2 to dout

Always @ (posedge CLK or negedge rst_n)

Begin

If (! Rst_n)

Dout <= 8'd0;

Else

Dout <= din1 + din2;

End

//-------------------------------------

// Self add addout

Always @ (posedge CLK or negedge rst_n)

Begin

If (! Rst_n)

Addout <= 4'd0;

Else

Addout <= addout + 1 'b1;

End

Endmodule

3) Compile, modify, and Debug. RTL is as follows:

4) create a new wave file and enter an incentive as follows:

5) simulation, complete, and output the simulation results as follows:

A) Four-byte clk_out

B) add the dout tool.

C) Auto-increment addout

2. Modelsim simulation function simulation

1) Same as above

2) Add 'timescale 1ns/1ns at the beginning of the wave_test code, that is, the simulation unit is 1ns, and the simulation precision is 1ns.

NOTE: If multiple files exist, timescale 1ns/1ns must be added for each file.

3) Same as above

4) Open Modelsim and create the wave_test_presynth project, as shown below:

A) SRC (the last one) is the directory for storing the source file of the Verilog us II design file.

B) simulation is the directory for storing Modelsim Projects

C) The presynth is the directory for saving the Modelsim function simulation file.

I. SRC is the directory for saving the testbench File

Ii. Work is the directory for saving project files

D) postsynth is the integrated functional simulation (this is not necessary for subsequent simulation design and backup, but for functional simulation only)

E) postlayout is the time series simulation after layout and wiring (subsequent simulation design is standby, only functional simulation is not necessary)

5) add file wave_test_tb.v to the testbench file, as shown in the following figure and code:

(When 'timescale 1ns/1ns is added, the simulation unit is 1ns, and the simulation precision is 1 NS)

'Timescale 1ns/1ns

Module wave_test_tb;

//-------------------------------

// Golobal clock

Reg CLK;

Reg rst_n;

// Divide clock

Wire clk_out;

// Adder Signals

Reg [7:0] din1;

Reg [7:0] din2;

Wire [7:0] dout;

// Self add data

Wire [3: 0] addout;

//-------------------------------

Wave_test u_wave_test

(

// Golobal clock

. CLK (CLK ),

. Rst_n (rst_n ),

// Divide clock

. Clk_out (clk_out ),

// Adder Signals

. Din1 (din1 ),

. Din2 (din2 ),

. Dout (dout ),

// Self add data

. Addout (addout)

);

//-------------------------------

// Initialization

Initial

Begin

CLK = 1' B0;

Rst_n = 1' B0;

#20 rst_n = 1' B1;

End

Always

#10 CLK =! CLK; // 20 NS, 50 MHz

//-------------------------------

// Input the Generator Excitation

Initial

Begin

#20 din1 = 8'h11; din2 = 8' H2;

#100 din1 = 8 'h33; din2 = 8' h44;

#500 din1 = 8'h55; din2 = 8' H66;

End

Endmodule

Of course, you can also create this file in Quartus to the directory or in Modelsim, as shown below

6) add exitiing files and add the Quartus SRC file as follows:

7) compile all error correction. If a double-click error occurs, the error prompt is displayed.

8) simulation-start simulation, select the wave_test_tb file in work as design units, and OK, as shown in the following figure (adding design units can also pre-compile the library file, as described in the next article; alternatively, right-click warm_test_tb in library-work, select simulation, or double-click it)

Loading wave_test_tb.v and wave_test has been performed. vsim 2> indicates waiting for the command.

9) Modelsim must complete the simulation to link all files. Therefore, after (8), add the following incentives. Open View-wave, and add the required input to the wave in view-objects's objects of wave_test_tb, which is similar to Quartus II. As shown in:

10) in the transcript window visim 2>, enter run 1000ns (running 1000ns), as shown below:

11) Click the dock/undock in the upper-right corner of the wave window to view the wave more conveniently, as shown in

The displayed hexadecimal format is the same as that of Quartus II.

12) reset simulation and end simulation (you can also use the Tcl script in transcript)

Other button functions are as follows:

13) to modify it, end the simulation, modify the code, compile, and run.

14) Try again. If not, try again. Just try again.