Use of ds1302 Chip

Pin functions and structure
Ds1302 pin arrangement, where vcc1 is the backup power supply, vcc2 is the main power supply. When the main power supply is off, the clock can also run continuously. Ds1302 is powered by a large user in vcc2. When the value of vcc2 is greater than that of vpc3 + 0.2v, vcc2 supplies power to ds1302. When vcc2 is smaller than vcc2.0, ds1302 is powered by vcc1. X1 and X2 are oscillator sources, with an external 32.768khz crystal oscillator. RST is a reset/Slice Line Selection. All data transmission is started by setting the RST input driver to a high level. RST input has two functions: first, RST connects the control logic and allows the address/command sequence to be sent to the shift register. Second, RST provides a means to terminate the transmission of single-byte or multi-byte data. When the RST is high, all data transmission is initialized and ds1302 can be operated. If the RST is set to low during transmission, the data transfer will be terminated, and the I/O pin will change to high-impedance mode. During power-on, RST must be kept low before VCC> 2.0v. RST can be set to a high level only when sclk is low. I/O is the output end of the serial data input (bidirectional), which is described in detail later. Sclk is the input of the clock.

Control byte of ds1302
The control word 2 of ds1302 is shown. The maximum valid bits (bit 7) of the control byte must be logical 1. If it is 0, data cannot be written to ds1302. If the value of bit 6 is 0, 1 indicates access to ram data, 5 to 1 indicates the address of the operation unit, and the lowest valid bit (0) if the value is 0, the write operation is required. If the value is 1, the read operation is performed. The control bytes are always output starting from the bytes.
　　
Data input/output (I/O)
When the rising edge of the next sclk clock after the command word input is controlled, the data is written to ds1302, and the data input starts from low to zero. Similarly, the ds1302 data is read along the descent edge of the next sclk pulse following the 8-digit control command, and the data is read from the low 0 to the high 7.
　　
Debugging problems
When ds1302 is used to exchange data with the microprocessor, the microprocessor first sends the command byte to the circuit. The highest bit write protect (D7) of the command byte must be logic 1. If D7 = 0, do not write ds1302, that is, write protection; D6 = 0, specify clock data, D6 = 1, specify Ram data; D5 ~ D1 specifies a specific register for the input or output. The memory LSB (D0) is logical 0, the write operation (input), The D0 = 1, and the read operation (output ).
Ds1302 must first send the command byte when transmitting data through the clock calendar or ram of ds1302. If single-byte transmission is performed, after the eight-bit command byte transmission ends, the rising edge of the next two sclk cycles is the input data byte, or the falling edge of the next eight sclk cycles is the output data byte.
Ds1302 Ram-related registers are divided into two categories: one is a single Ram unit, a total of 31, each unit is configured as an 8-bit byte, its command control word is c0h ~ FDH, where the odd number is the read operation and the even number is the write operation. The second type is the ram register in the burst mode. In this mode, 31 bytes of all RAM can be read and written at a time.
Note that the backup power B1 can be battery or super capacitor (0.1f or above ). Although ds1302 consumes a small amount of power after the power of the main power supply is down, it is best to use a small rechargeable battery if you want to ensure the clock is normal for a long time. You can use the 3.6v rechargeable battery on an older computer motherboard. If the power-off time is short (several hours or several days), it can be replaced by a common electrolytic capacitor with less leakage. 100 μF can ensure a normal 1 hour walk. Ds1302 Initialization is required after the first power-on. After initialization, you can adjust the time according to the normal method.
　　
FAQ description:
1. the time can be written into the ds1302 chip, but the time is inconvenient to maintain
1) when the time does not go, first check whether the maximum ch of the Miao register (81 h) is 1, which is used to control whether the crystal oscillator stops vibration, 0 crystal oscillator to normal vibration;
2) If the CH position is 0 and the crystal oscillator is not vibrating, check whether the crystal oscillator is reverse, whether the circuit is correct, and whether the crystal oscillator is damaged.

2. data cannot be written.
Checks whether the highest bit of the WP write Protection Register (8fh) is 1. If the highest bit is 1, the write protection status is enabled.

3. Unable to charge
The power-on charging function of ds1302 is disabled. When detecting the charging control register (91 H), the charging conditions are as follows:
1) The TCS value is 1010 h, and the charging function is disabled for other values;
2) If DS is 01, 1 diode is selected, DS is 10, 2 diodes are selected, and charging is disabled;

3) RS is 01, 2 k Ω resistance is selected, RS is 10, 4 k Ω resistance is selected, RS is 11, 8 k Ω resistance is selected, RS is 00, the charging function is disabled.

4. There is no problem with waveform analysis captured through the oscilloscope, but the RTC cannot be read and written normally.

If there is no problem with reading and writing the timing through the oscilloscope, but the data written to ram is not correct after reading, and the time cannot be set, you have to suspect that the chip is faulty, there are many fake chips in China on the market. The timing sequence may be inconsistent with the datasheet sequence officially provided by ds1302. You can buy an imported chip to replace it.