Use the download cable to implement the HTTP interface programming function of the source instance, which is *. *.

This article Reprinted from: http://www.infomcu.com/Program/20071007/455_2.html

 

Abstract:Download cables are widely used in the design and debugging of electronic systems. This article introduces its basic principles and programming control methods. For the list instances of the current single-chip microcomputer's ISP serial programming mode, it briefly introduces the serial programming method and part of the protocol of at89s5x, using VC programming, the application download cable implements the ISP programming for the at89s5x series single-chip microcomputer. At the end of this article, we propose the idea of uniformly downloading the hardware or software of the single-chip microcomputer, and provide the website that supports downloading a variety of single-chip microcomputer ISP programming software.

Keywords:Download the serial programming of the cable. *

Introduction

With the development of electronic technology, the chip size is growing and the encapsulation size is becoming smaller and smaller, and the difficulty in system board-level debugging is also increasing. IEEE has developed the standard IEEE Std 1149.1 for standard test port and boundary scan, which is the JTAG interface protocol. The JTAG interface uses four signal lines: TCK, TDI, TDO, and TMS to provide connectivity tests for various pins of the complex chip in serial mode, the progress also enables the configuration of the programmable chip and debugging of the processor chip. Download cable is a cheap tool that uses the parallel port of a computer to implement the JTAG interface protocol through the imitation zero point of the software and access the programmable chip. The download cable used in this article is the byteblastermv cable developed by Altera for its programmable logic devices. ISP (short for System Programming) is a technology first proposed by lattice, which is to reconfigure its programmable logic devices in synchronous serial mode. ISP and JTAG interface protocols are very similar, but the latter forms a standard. ISP has now become a concept. Its proposal has changed the development process of traditional hardware systems, greatly facilitating developers and speeding up development. Most programmable devices (FPGA, CPLD, DSP, MCU ......) ISP features are supported. Single-chip microcomputer is no exception, at89s series 51 Single-Chip Microcomputer launched by ATMEL also conforms to ISP characteristics.
 
1. download cable hardware

Dedicated IC can be used to implement the JTAG interface protocol, such as 74lvt8980 and 74lvt8990. It works with MCU to provide high-speed JTAG serial access at a high cost. Downloading cables is a cheap solution to implement the JTAG interface protocol. It only uses 74hc244 as the line drive, and the computer's parallel port leads to I/O as the signal lines such as TCK, TDI, TDO, and TMS. Since the parallel port has three ports in spp mode: data output port, control output port, and STATUS input port, the JTAG signal lines derived from various download cables are almost different, figure 1 and figure 2 are the schematic diagrams of the two download cables.

Parallel introduction:

The parallel port of a computer works in spp mode, and its control is implemented through the data output port, control output port, and State input port.

The parallel port has 25 pins, including 8-bit data lines, 5-bit status lines, and 4-bit control lines.

Data port (378 h): D0 ~ D7 is used for data output.

Status ports (379 h): * S7 (busy), S6 (NACK), S5 (PE), S4 (select), and S3 (nerror ).

Control port (37ah): * C3 (nselin), S2 (ninit), * C (anutofeed), and * C0 (nstrobe ).

() (The port address is the default LPT1 setting; * indicates that this pin has a reverser)

Table 1 defines parallel ports. The corresponding schematics include:

Altera download cable

TCK, TDI, TMS, and TDO correspond to D0, D6, D1, and * S7 respectively;

ATMEL Cable

TCK, TDI, TMS, and TDO correspond to * C0, D0, * C3, and S6 respectively.

　　Table 1 parallel port Definitions

Pin No.	Name	Data bit
1	Nstrobe	* C0
2	D0	D0
3	D1	D1
4	D2	D2
5	D3	D3
6	D4	D4
7	D5	D5
8	D6	D6
9	D7	D7
10	Nack	S6
11	Busy	* S7
12	PE	S5
13	Select	S4
14	Auto feed	* C1
15	Nerror	S3
16	Ninit	C2
17	Nselin	* C3
18 ~ 25	Gnd	Gnd

2 programming method for download cable

The JTAG protocol is implemented using the download cable controlled by the computer, which is to perform read and write operations on the three I/O Ports of the parallel port. The JTAG sequence is simulated with 0-1 changes. The driver is required to read and write I/O in WIN98 and win2000 environments. This article uses driverlinx port I/O Driver (which can be downloaded from www.sstnet.com) to implement access to the I/O port. After dlportio is installed, call the dynamic Connection Library

Uchar dlport_api d1portread portuchar (in ulong port );

Void dlport_api d1portwrite portuchar (in ulong port, in uchar value); the two functions can access the 378 H, 379 H, and 37ah (this is the default LPT1 setting) three Parallel Port I/O Ports. In section 1, a level value is assigned to the Altera download cable:

Procedure 1

Altera download cable level assignment function

Void cavrispdlg: setbit (){

Unsigned char value = 0;

If (! M_tck) value | = 0x01;

If (! M_tms) value | = 0x02;

If (! M_tdi) value | = 0x40;

Dlportwriteportuchar (0x378, value );

Value = dlportreadportuchar (0x379 );

If (Value & 0x80) m_tdo = 0;

Else m_tdo = 0;

}

By changing the I/O status of each JTAG interface in turn using the above program, simulating the time sequence of the JTAG protocol, you can access various chips that support the JTAG Standard.

3 ISP Protocol Resolution and implementation

Use the SPI Synchronous Serial Interface Protocol instead of the JTAG protocol for the issps programming of the at89s5x series single-chip microcomputer, as shown in 3.

We use arrays to simulate the timing of the 8-bit SPI interface protocol, such as needle:

The clock signal is fixed to unsigned char sck [19] = };

The output data signal is automatically generated by the Program Implementation of the array unsigned char MoSi [19];

The input data generates the array unsigned char miso [19] based on the read signal.

Call the setbit () function above to send the 19-bit JTAG interface I/O status in sequence, and read the returned signal at the same time to complete a single-byte access to the SPI of the at89s5x chip.

On the basis of single-byte access, refer to the Instruction format in the serial programming instruction table in the at89s5x Data Manual of ATMEL to implement ISP.

Table 2 is the serial programming instruction table.

　　Table 2 serial programming instruction set

Orders	Model				Description
	1st bytes	2nd bytes	3rd bytes	4th bytes
Programming enabling	10101100	01010011	XXXXXXXX	XXXXXXXX	Enable serial Programming
Chip Erasure	10101100	100 XXXXX	XXXXXXXX	XXXXXXXX	Erased program storage
Read program bytes	00100000	Xxxxa11 ~ A8	A7 ~ A0	D7 ~ D0	Byte read Program
Write Program bytes	01000000	Xxxxa11 ~ A8	A7 ~ A0	D7 ~ D0	Write programs in byte mode
Write protection bit	10101100	111000b1b2	XXXXXXXX	XXXXXXXX	Write protection bit
Read protection bit	00100100	XXXXXXXX	XXXXXXXX	Xxlb3 ~ Lb1xx	Read Current Protection bit
Read flag bytes	00101000	Xxxa5 ~ A1	A0xxxxxx	Flag data	Read flag data
Read program page	00110000	Xxxxa11 ~ A8	DATA 0	Data 1... 255	Page mode read Program
Write Program	01010000	Xxxxa11 ~ A8	DATA 0	Data 1... 255	Write programs in page Mode

Note: ① serial programming should be implemented when the RST side is connected to a high level; ② X indicates this bit of concern; ③ A11 ~ A0 is the byte address to be accessed; ④ D7 ~ D0 is read/write data; ⑤ B1 and B2 are protective bits; ⑥ lb3 ~ LB1 indicates three statuses.

For the AT89S51 microcontroller, the mark bytes are: (00 h) 1eh, (02 h) 51 h, (04) 06 h.

Program segment 2 will get the flag byte of the AT89S51 microcontroller. (Spicomm () is a single-byte SPI access function ).

Procedure 2

Obtain the program segment of the single-chip microcomputer sign byte

Cstring STR;

For (ADDR = 1; ADDR <3; ADDR ++ ){

M_comm = 0x28;

Spicomm ();

M_comm = ADDR;

Spicomm ();

M_comm = 0;

Spicomm ();

M_comm = 0;

Spicomm ();

Str. Format ("0x % 02x", m_dat );

M_out + = STR;

}

Figure 4 is the hardware schematic diagram of the serial programming of the AT89S51.

4. Summary

The download cable provides us with a deep chip in our hands. With the JTAG Standard protocol, we can use the download cable to check chip welding connectivity, reconfigure programmable devices, download program firmware, and debug processor operations.

Serial programming of 8-Bit Single-Chip Microcomputer, download cables can be seen in the configuration of tens of thousands of FPGA chips. For example, arm can use the JTAG simulation of the download cable to develop and debug arm through the embeddedice interface, or use the arm Boundary Scan feature to download the Startup Program for the embedded system board.

Currently, more and more download cables are used. Various manufacturers have released their own JTAG-compliant chips or new products using ISP technology. At the same time, there are many types of download cables, most of which differ only in the correspondence between the parallel port signal and the JTAG signal. Sometimes a product needs to be developed using many different cables. We hope that we can use a standard download cable to implement all the JTAG applications, or a computer program can use various download cables through the configuration file. In our blmvisp software, two existing cables are supported.

ISP technology can greatly accelerate hardware development. The combination of download cables and computer software can also reduce development costs and is suitable for individual enthusiasts and beginners.

Interested readers can download the blmvispdemo vcsource Program Package (demo_blmvisp.zip) for reference; can also access: http://51kaifa.nease.net or email: blmv@eyou.com.