[Vc6] Checks support levels for MMX and SSE Series Instruction Sets (up to sse4.2)

References --
Intel 64 and IA-32 ubuntures software developer's Manual Volume 2 (2a, 2b & 2c): Instruction Set Reference, A-Z. December 2011. http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.html
Intel processor identification and the cpuid instruction. January 2011. http://developer.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html
Amd64 architecture programmer's Manual Volume 3: General purpose and system instructions. December 2011. http://support.amd.com/us/Processor_TechDocs/24594_APM_v3.pdf
AMD cpuid specification. September 2010. http://support.amd.com/us/Embedded_TechDocs/25481.pdf
Http://en.wikipedia.org/wiki/CPUID

 

Running Effect --

 

The Code is as follows --

// The Return Value of the level. simd_sse_level function supported by the SSE Series Instruction sets.
# Define simd_sse_none 0 // not supported
# Define simd_sse_1 1 // SSE
# Define simd_sse_2 2 // sse2
# Define simd_sse_3 3 // sse3
# Define simd_sse_3s 4 // ssse3
# Define simd_sse_41 5 // sse4.1
# Define simd_sse_42 6 // sse4.2

Const char * simd_sse_names [] = {
"None ",
"SSE ",
"Sse2 ",
"Sse3 ",
"Ssse3 ",
"Sse4.1 ",
"Sse4.2 ",
};


// Whether the MMX instruction set is supported
Bool simd_mmx ()
{
Const DWORD bit_dx_mmx = 0x00800000; // bit 23
DWORD v_edx;

// Check processor support
_ Try
{
_ ASM
{
MoV eax, 1
Cpuid
MoV v_edx, EDX
}
}
_ Handler T (exception_execute_handler)
{
Return false;
}
If (v_edx & bit_dx_mmx)
{
// Check OS support
_ Try
{
_ ASM
{
Pxor mm0, mm0 // executing any MMX instruction
Emms
}
Return true;
}
_ Handler T (exception_execute_handler)
{
}
}
Return false;
}


// Check the support level of SSE instruction sets
Int simd_sse_level ()
{
Const DWORD bit_d_sse = 0x02000000; // bit 25
Const DWORD bit_d_sse2 = 0x04000000; // bit 26
Const DWORD bit_c_sse3 = 0x00000001; // bit 0
Const DWORD bit_c_ssse3 = 0x00000100; // bit 9
Const DWORD bit_c_sse41 = 0x00080000; // bit 19
Const DWORD bit_c_sse42 = 0x00100000; // bit 20
Byte RT = simd_sse_none; // result
DWORD v_edx;
DWORD v_ecx;

// Check processor support
_ Try
{
_ ASM
{
MoV eax, 1
Cpuid
MoV v_edx, EDX
MoV v_ecx, ECx
}
}
_ Handler T (exception_execute_handler)
{
Return simd_sse_none;
}
If (v_edx & bit_d_sse)
{
RT = simd_sse_1;
If (v_edx & bit_d_sse2)
{
RT = simd_sse_2;
If (v_ecx & bit_c_sse3)
{
RT = simd_sse_3;
If (v_ecx & bit_c_ssse3)
{
RT = simd_sse_3s;
If (v_ecx & bit_c_sse41)
{
RT = simd_sse_41;
If (v_ecx & bit_c_sse42)
{
RT = simd_sse_42;
}
}
}
}
}
}

// Check OS support
_ Try
{
_ ASM
{
Xorps xmm0, xmm0 // executing any SSE instruction
}
}
_ Handler T (exception_execute_handler)
{
Return simd_sse_none;
}

Return RT;
}

Int main (INT argc, char * argv [])
{
Int I;
Bool bmmx = simd_mmx ();
Int nsse = simd_sse_level ();
Printf ("MMX: % d \ n", bmmx );
Printf ("SSE: % d \ n", nsse );
For (I = 1; I <sizeof (simd_sse_names); ++ I)
{
If (nsse> = I) printf ("\ t % s \ n", simd_sse_names [I]);
}

// Wait
Getch ();
Printf ("\ n ");
Return 0;
}

 

Download source code --

Http://files.cnblogs.com/zyl910/checksimd.rar