Verilog Odd-frequency design

Module TW (CLK,K_OR,K1,K2);

Input CLK;

Output K_OR,K1,K2;

reg [2:0] c1,c2;

Reg M1,M2;

Initial

Begin

c1=0;

c2=0;

m1=0;

m2=0;

End

Always @ (Posedge CLK)

Begin

if (c1==a) C1<=0;else c1<=c1+1;

if (c1==1) M1=~m1;else if (c1==b) m1=~m1;end

Always @ (Negedge CLK)

Begin

if (c2==a) C2<=0;else c2<=c2+1;

if (c2==1) M2=~m2;else if (c2==b) m2=~m2;end

Assign k1=m1;

Assign k2=m2;

Assign k_or=m1|m2;

Endmodule

Divide coefficient, the following formula is used

a=n-1;

B=n-2;

n is the divide factor.

Verilog Odd-frequency design