VHDL generated NGC file was Verilog by the engineering call problem

1. The question was raised

Project A is a soft core, written in VHDL, the synthesis of the time to remove the "Add I/O buffers", and-IOB (Pack I/O registers into Iobs) set to No. The A.NGC file was finally generated for use by other projects. After NGC is generated, the appropriate call file can also be generated in the View HDL instantiation Template "Design Utilities".

Project B calls the A.NGC, but Engineering B uses Verilog to write, and at the time of invocation there was an error in finding the A module.

2. How to solve a problem

Use the Netgen command to convert the NGC to a VHDL or Verilog file, and then after invoking the converted File

Linux under

Netgen--ofmt VHDLFILENAME.NGC

Windows under

Netgen.exe--ofmt VHDLFILENAME.NGC

3. Solution to the problem B

The above approach is only a trickery approach, and a better approach is achieved through the use of wrapper files.

Assuming that the original NGC file is ABC.NGC, its wrapper file is named ABC.V or ABC.VHD. This wrapper file only declares the input and output ports of the ABC module and does not contain additional information.

A simple way to generate a wrapper file is to use the Netgen tool mentioned in solution A to delete other statements using Netgen generated Verilog files or vhdl files, leaving only their declarations.

You can then add both the wrapper file and the NGC file to the project.

VHDL generated NGC file was Verilog by the engineering call problem