VHDL Port Map mapping occurs when 1166052warning-logical net ' Clkin ' has no load.

When using lattice Domiand, the following illustration appears, an input signal always appears in the unconnected column, meaning that you cannot bind the pins.

Logical net ' Clkin ' has no load.

Input pad NET has no legal load.

This is a warning, but your functionality will not be tested properly.

After several times of repeated examination of the code, and did not find that the PIN code has a logical problem, or have been optimized problems.

Finally, I found that my code makes the generated SCH file interconnect in the schematic diagram. The module pins containing this signal cin are not all painted with input/output terminals. And the problem is out here ...

Because for example you only connect the input, in the synthesis, the compiler will check the input and output, when in this module, only detect input, and no output, the programmer defaults to the useless input pins to kill, so you that signal foot into the unconnected.

So make sure that all your pins are connected, unless you're pretty sure that the disconnected pins have no effect on the logical optimizations.