What is boundary scan )?

Boundary Scan (Boundary Scan) is a testing technique proposed when traditional online testing is not suitable for large-scale, high-integration circuit testing, the shift register is placed between the internal logic of the IC and the pins of each device during the icdesign process ). each shift register is called a cell. These cells allow you to control and observe the status of each input/output pin. When these cells are connected together, a data register chain is formed, which is called boundaryregister ). In addition to the above shift register, the Test Access Port Controller is also integrated on the IC.
(TAP controller), the instruction register (instruction register) decodes the instruction of the boundary scan to perform various test functions. The bypass register (bypass register) provides a shortest path. In addition, idcode register and other user-defined special registers may be available.


The typical features of the border scanner and the composition of the border scan test signal.


If a device is a border scanner, it must have the first four of the following five signals:

1. TDI (Test data input)

2. TDO (side test data output)

3. TMS (select input in test mode)

4. TCK (test clock input)

5. trst (test reset input, this signal is optional)


TMS, tck, and trst constitute the border scan test port controller, which is responsible for testing the input, output, and Instruction Decoding of signal commands. the TAP controller is a 16-bit state machine, each step of the border scan test is controlled by it, so you must have a clear understanding of the TAP controller.

In subsequent articles, we will introduce other aspects of border scan.

Boundary Scan shortens the development cycle for developers and provides good coverage and diagnostic information. Do not understand

Quickly develop excellent test programs in the case of IC internal logic. In the future testing field, border scanning will be widely used.Certificate -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Boundary scanning testing was developed in the 1990s S. With the emergence of large-scale integrated circuits, the manufacturing process of printed circuit boards is becoming small, micro, and thin, traditional ICT testing cannot meet the testing requirements of such products. Due to the many pins of the chip, the small size of the components, the density of the board is very large, there is no way to test the probe. A new test technology is developed. The joint test behavior Organization (joint test action group), JTAG for short, defines this new test method, namely, border scan testing.

Included by the International Electrotechnical Commission as IEEE1149.1-1990 boundary scan test access port and boundary scan structure standards. This Standard specifies the hardware and software required for the boundary scan test. After its approval in April 1990, IEEE supplemented the standard in April 1993 and April 1995 to form the ieee1149.1a-1993 and ieee1149.1b-1994 currently in use. JTAG is mainly used for: Circuit boundary scan testing and online system programming of programmable chips.

JTAG was officially standardized by IEEE's Document 1990-1149.1 in 1990. In 1994, JTAG added a supplementary document to describe the border scan Description Language (bsdl. Since then, this standard has been widely used by electronic enterprises around the world. Border scan is almost synonymous with JTAG.

At present, the secondary block used to test the integrated circuit is used in the design of the printed community edition. It also provides a useful debugging mechanism for embedded systems and a convenient "backdoor" in the system ". When some debugging tools are used as signal transmission mechanisms by using JTAG in circuit simulators, programmers can read the debugging modules integrated into the CPU through JTAG. The debugging module allows programmers to debug software in embedded systems.

Edge scanning testing was developed in the middle of 1980s as a JTAG interface to solve the problem of physical access to the PCB. This problem was caused by the increasingly crowded assembly of the Board due to the new packaging technology. The Boundary Scan embeds a test circuit at the chip level to form a comprehensive circuit board-level test protocol. Using Boundary Scan-industry standard IEEE 1990 since 1149.1-you can even test, debug, Program on system devices, and diagnose hardware problems in the most complex assembly.

By providing Io access to the scanning chain, you can eliminate or greatly reduce the need for physical test points on the board, which significantly saves costs, because the circuit board layout is simpler, the test fixture is cheaper, the test system in the circuit takes less time, the use of standard interfaces increases, and the time to market is faster. In addition to circuit board testing, boundary scan allows programming almost all types of CPLD and flash memory on the Board after a PCB patch, regardless of the size or encapsulation type. In system programming, you can save costs and increase production by reducing device processing, simplifying inventory management, and integrating programming steps on the circuit board production line.

The IEEE 1149.1 Standard specifies a four-line serial interface (the fifth line is optional), called a Test Access Port (TAP), used to access complex integrated circuits (IC ), such as microprocessor, DSP, ASIC, and CPLD. In addition to the TAP, the Hybrid IC also contains the shift register and the state machine to perform the Boundary Scan function. Data entered into the chip on the TDI (test data input) lead is stored in the instruction register or in a data register. Serial Data leaves the chip from the TDO (test data output) lead. The Boundary Scan logic timing signals on the TCK (test clock) and the TMS (Test Mode Selection) signal drives the status of the TAP controller. Trst (test reset) is optional. On the PCB, you can connect multiple ICs that are compatible with the scanning function to form one or more scanning chains. Each chain is associated with its own tap. Each scan chain provides electrical access, from the serial tap interface to each lead on each IC as part of the chain. During normal operation, the IC executes its predefined function, as if the Boundary Scan Circuit does not exist. However, when device scan logic is activated for testing or system programming, data can be transmitted to the IC and read from the IC using a serial interface. In this way, the data can be used to activate the device core, send the signal from the device lead to the PCB, read the PCB input lead and read the device output.