"Xiaomei SOPC Study notes" Sof with Nios II elf firmware merge Jic get file

SOF with Nios II elf firmware merge Jic get file 7.1 Why need to merge SOF with Elf to get JIC file

When we study and debug the Nios II project, we typically use the Quartus programmer provided in the Quartus II software to burn the FPGA configuration file (SOF) and then nios the flash provided in the II EDS Programmer tool to burn write Nios II. This is not inconvenient for developers, but because of the flexibility of this way, for the development of a great convenience. However, when our products have been designed and produced, it is necessary to burn the firmware into the product. When burning on a production line, you always want to be able to do it in the simplest way possible. Imagine, if the production line on the burning, but also need a few tools to change, waiting for a long time, the efficiency of the natural go down. So this quartus Programmer+flash Programmer Way is not suitable for production.

In his recent work, Brother Mei also encountered such problems. Our new design of a number of development boards, after the factory production, are to carry out factory testing. However, SMT manufacturers are not familiar with our quartus Programmer+flash Programmer burning writing method. Besides, to use this method, Quartus programmer and Nios II eds software are also installed. Manufacturers say the use of this method is difficult for them, and the efficiency is not high. So I made a conversion based on a post on Altera's official website, merging the SOF file with the ELF firmware of Nios II and generating a JIC file so that the manufacturer would only need to use Quartus Programmer to burn this JIC file will enable the simultaneous burning of FPGA configuration files and Nios II firmware, simplifying steps and saving time.

The original address of the JIC file obtained from the SOF file and Elf file is as follows:

Https://www.altera.com.cn/support/support-resources/knowledge-base/solutions/rd10132010_126.html

7.2 Examples of this chapter describe

Because of the experience of the friend reflected in this tutorial after watching the course still do not know how to operate, always unsuccessful, so this is the use of our core Route FPGA Development Board, step by step demonstration of this implementation process, the entire process is materialized.

Let me explain the structure of this design project:

EPCS16 : the firmware used to store the FPGA configuration file and the Nios, and in this case the resulting JIC file is also burned to the device.

512K byte SRAM: as Nios II or 4.3 inch TFT memory, here as the TFT memory. (PS: Using SRAM as the storage, compared with the use of SDRAM as the storage, NIOS II performance will be significantly improved.) ）

128Mbit SDRAM : as Nios II or 4.3 inch TFT memory, here as Nios II deposit. To run a more complex program or GUI.

4.3 inch TFT: used to display text/pictures and other content.

XPT2046 Touch Controller: use SPI interface to get touch screen information, realize human-computer interaction

CH340 Usb2ttl : the UART protocol and the USB protocol are converted to each other. To implement the debugging functionality.

4bit LED : Indicates the program running state.

2X tap the key: Enter control information

After the system is introduced, the entire conversion process can be introduced:

7.3 Detailed conversion Steps 7.3.1 Sof2flash:

Generate a flash file from a. sof file:

Sof2flash--input=

First we open our Nios II software engineering and the corresponding board level support package, which is named Tft_touch and tft_touch_bsp

Then select Tft_touch, right-click to select Nios II--Nios II Command Shell

Our Quartus II produces the SOF file named "Tft_sram.sof", this time, if we enter directly

Sof2flash--input= tft_sram.sof--output=hwimage.flash--epcs–verbose

You will be prompted to find the input file that is not found in the tft_sram.sof.

This is because the command is looking for the Tft_sram.sof file under the current directory, and our Tft_sram.sof file is in the E:\easy_sopc\TFT_SRAM\prj\output_files directory, so of course we can't find the file. There are two ways to solve this problem.

The first, recommended program.

Because many friends who are unfamiliar with the command line are slow and error-prone when they operate, this provides a familiar way to do so. First, in Windows, copy the Tft_sram.sof file from the Output_files folder to the Tft_touch folder:

Then go back to the command line window and execute it again

Sof2flash--input= tft_sram.sof--output=hwimage.flash--epcs–verbose command

(Tip: Using the UP ARROW key on the keyboard, you can quickly switch to the previously used command, where after you switch the directory, you should be able to find the previously entered Sof2flash command by pressing the key two times.) The build process takes about 10 seconds. After the build is complete, it looks like this:

We then enter the LS command to see that a file named Hwimage.flash is actually generated:

The second scenario: first use the CD command in the shell to switch directories directly to the directory where the SOF files are located, that is, E:\easy_sopc\TFT_SRAM\prj\output_files. The corresponding command is (note the slash direction):

CD E:/easy_sopc/tft_sram/prj/output_files

Then execute the sof2flash command again. After the build is complete, it looks like this:

We then enter the LS command to see that a file named Hwimage.flash is actually generated:

Generally recommend that you use the first way, of course, except the command line master.

7.3.2 Elf2flash:

From one, Elf generates a Flash file:

Elf2flash--input=<elf file>.elf--output=swimage.flash--epcs--after=hwimage.flash--verbose

Because it is recommended to use the first way, so here is the first way to go on, believe that the ability to switch directories with the command line of friends, there is no problem with other operations.

Here we just need to enter the Elf2flash command directly, the command details are as follows:

Elf2flash--input=tft_touch.elf--output=swimage.flash--epcs--after=hwimage.flash–verbose

As you can see from the command, the Hwimage.flash file generated by the first step is part of the parameter, so you must ensure that the Hwimage.flash is in the current directory. (This is automatically ensured by using the recommended method in the first step). The command execution results are as follows:

Then we enter the LS command, and we can see that a file named Swimage.flash is actually generated under the current folder:

7.3.3 Flash2hex:

Convert. flash files to. hex Files: Enter the following commands directly (note: Altera official website This place command is wrong, before and after correspondence, the original post for nios2-e ... Mysw.flash Mysw.hex, should say MYSW instead swimage):

Nios2-elf-objcopy--input-target srec--output-target ihex swimage.flash Swimage.hex

This command is executed in an instant, we can see that a Swimage.hex file has been generated under the current folder under LS:

7.3.4 Convert Programming Files

In Quartus? II software, open File > Convert programming Files > Set the programming file as JTAG Indirect Configuration file (. jic).

7.3.5 Select EPCs

Select the appropriate size EPCs device in the Configuration drop-down menu (see 10 Step chart)

7.3.6 named Jic

Name your output. jic file (see 10 Step chart)

7.3.7 ADD Device

Click below the flash loader and select Add Device on the right (see 10 step chart)

7.3.8 Selecting FPGA Devices

Select your FPGA device from the list (see 10-Step chart)

7.3.9 Add SOF

Click on SOF Data, select Add File, select Add. sof file (see 10 Step chart)

7.3.10 ADD Hex Data

Click Add Hex data, select relative addressing, select the. hex file generated above

7.3.11 Generate

Then click Generate Build. After the build is complete, check the generated. map file (open with Notepad) with the start address of the Page_0 at the start address 0x0,.hex file after the Page_0 end address 1

7.3.12 Burn Write

Now in Quartus II programmer, select Add File and select Add. jic files. Check the program box, next. jic file, then press start.

7.3.13 test Results

Finally on a test map, goddess of the town building (say that a picture to the customer, customers will feel particularly happy it):

If you have more questions, welcome to join the core Route FPGA Technology Support Group Exchange Learning: A group of 472607506 (full) two group 615381411

Brother Mei

Core Route Electronic Studio

"Xiaomei SOPC Study notes" Sof with Nios II elf firmware merge Jic get file