Will proceed from the next instruction
Debug Programs
Abnormal abort
Forcing the affected process to terminate
There's been a serious mistake.
Four, IRQ
1. The hardware Device controller interrupts the CPU through the IRQ line, and can be shielded from interruption by disabling an IRQ line.
2. Prohibited interrupts will not be lost, after activating IRQ, interrupts will also be sent to the CPU
3. Activate/disable IRQ line!= Global Shield/non-masking for
:2000.336Cache size:512 KBFdiv_bug:noHlt_bug:noF00f_bug:noComa_bug:noFpu:yesFpu_exception:yesCPUID level:1Wp:yesFLAGS:FPU VME de PSE TSC MSR PAE MCE cx8 APIC Sep MTRR PGE MCA cmov Pat PSE36 Clflush MMX fxsr SSE SSE2 syscal L NX mmxext fxsr_opt lm 3dnowext 3dnow up PNI lahf_lm ts FID vid TTP TM STCbogomips:4002.57
The above information shows that this is an AMD Athlon 64 3200+ CPU.
CPU tuning parameters can be obtained from the following address (som
Resolve | Problem Mandrake 9.0 APIC (Advanced Programmable Interrupt Controller) causes USB etc. not to be normal, even cause system deadlock. Very serious!! The solution is simple: Just add the Noapic parameter to the LILO command line. Like what:
Lilo:linux Noapic
With GRUB's friends, you should add noapic parameters to the kernel command line (for example, add to the tail of the kernel line).
Sorry, this is not the original translation, but it is
NT CPUs to increase scalability. 100 101 5. Configuring a driver to use Msi/msi-x 102 with default, the kernel would not enable msi/msi-x on all devices Pport this capability. The Config_pci_msi Kernel option must is selected to enable msi/msi-x support. The 5.1 including msi/msi-x support into the kernel 108-109 to allow-msi/msi-x capable device to drivers Enable Msi/msi-x (using Pci_enable_msi ()/pci_enable_msix () as described below), the VECTOR based scheme needs to
Be-enabled by setting 1
We can get the information we need in/proc/cpuinfo.
1. The current CPU model
[root@ localhost ~]# cat/proc/cpuinfo |grep ' model name ' |uniq
Model NAME:AMD Opteron (tm) Processor 6140
2. Current CPU operating mode
[Root@localhost tmp]# getconf Long_bit
32
Indicates that the current CPU is running in 32-bit environments
3. Whether the current CPU supports 64-bit environments
[root@ localhost ~]# cat/proc/cpuinfo |grep ' lm ' |uniq
FLAGS:FPU VME de PSE TSC MSR PAE MCE cx8
exception, and an asynchronous interrupt is called an interrupt.
Exceptions are divided into: fault (fault) traps (TRAP) abort (abort).
Failure: Notifies the exception of an exception to the system before the instruction that caused the failure. Go back to the original position and continue.
Traps: Svc
Abort: Notifies a system of an exception when a system is in serious condition. The command that caused the abort is unpredictable. The execution is not recoverable when the abort occurs.
Se
Tags: new src enable VMware War VMDK warning process windowsThe default image format for VMware is. vmdk format, and VirtualBox is the default. VDI format. In fact, this is optional in the process of VirtualBox a new virtual machine.Importing. VMDK-formatted mirrors to VirtualBox only requires a new virtual machine and does not create a virtual hard disk. Such as:Ignore the warning and continue:Once created, add the virtual hard disk in the. vmdk format to the settings:That's all you can do.If y
Turn on vsphere's SSH telnet service orReference:https://kb.vmware.com/selfservice/microsites/search.do?cmd=displayKCdocType=kcexternalId=2075199Step Two: Modify the configurationShutting down a virtual machineLog in to the ESXi ShellFind a virtual machine configuration file[[Email protected]:~] Find/-name *.VMX/vmfs/volumes/570794cb-7a2de328-398b-000c294ee9b7/centos7/centos7.vmxModify the configuration file (add vhv.enable = "TRUE" on the last line of the configuration file)Note You cannot have
Atitit. Get Connection Hibernate41. Sessionfactoryutils method (Recommended ) 12. ConnectionProvider Law (1 )3. GA self-Implementation ( not recommended ) read HB configuration file 14. Or use work (but the working black Conn is a closure, not good for use) 11. Sessionfactoryutilsmethod (recommended ) Multiple conn generated by this method are actually one , so it's not good to useHibernate3.3.2 version getsession (). Connection () has been deprecated, alternative method Sessionfactoryutils.getd
multi-processing support supports multi-processor options. If you only use a single CPU, disable it.
04.07,
Preemptible Kernel is a new feature. As mentioned in almost all articles about 2.6, This is the preemptive Kernel. That is to say, some high-priority programs can first execute with some low-priority programs, even if these programs are executed in the core State (which is actually not really a preemptive kernel ). This reduces the kernel latency and improves system response. Of course,
In Linux, view the cpu information-general Linux technology-Linux technology and application information. The following is a detailed description. View cpu information:
[Junjie2 @ ljj ~] $ Cat/proc/cpuinfo
Processor: 0
Vendor_id: GenuineIntel
Cpu family: 6
Model: 13
Model name: Intel (R) Pentium (R) M processor 1.60 GHz
Stepping: 8
Cpu MHz: 1592.106
Cache size: 2048 KB
Fdiv_bug: no
Hlt_bug: no
F00f_bug: no
Coma_bug: no
Fpu: yes
Fpu_exception: yes
Cpuid level: 2
Wp: yes
Flags: f
necessary. When something in M changes, C needs to understand these changes. How can we let C know m changes? Notification and KVO are good solutions to the problem. They work like this. When something in M changes, they will send a notification to C, "Hey, dude, attention, I have changed ", or they will send a pointer pointing to a change to C, or something else. In short, they work like this.
The following is a summary. Cocoa is loyal to MVC, so it is our key start to understand cocoa MVC. I
to switch to PM or SMM ). When the host is powered-up or reset, the processor is in RM.
SMM is a standard architecture feature for all Intel processors. It appears on the intel386 SL chip. This mode provides a transparent mechanism for the OS to implement the functions specified by the platform (such as power management or system security. When an external SMM interrupt pin (SMI #) is activated or an SMI is received from the APIC (Advanced Programmin
functions are implemented through IO port read/write.
SoftICE replaces the following interrupt (TRAP) handlers in the IDT table:
0x1: One-Step trap Handler0x2: NMI unshielded interrupt0x3: debug the trap Handler0x6: Invalid operation code trap Handler0xb: Segment does not have a trap Handler0xc: Stack error trap Handler0xd: general protective error trap Handler0xe: Page error trap Handler0x2d: debug the service trap Handler0x2e: System Service trap Handler0x31: 8042 keyboard controller inter
menu under your drive C. modify vmlinuz and initrd. imgfile path and name, and modify the UUID. If it is an ext4 partition, add the rootfstype = ext4 parameter. Because the APIC in my notebook seems to be a little faulty, The ACPI = off noapic nolacip parameter should not be added to most people, so we do not need to add these three parameters.
Now, restart. Select grub in the operating system list and then ubuntu9.10. You should be able to access yo
View Linux Server CPU
Two Guiding Principles
# CPU with the same core ID is hyper-threading of the same core #
# A cpu with the same physical ID is a thread or core encapsulated by the same CPU #
CAT/proc/cpuinfo | grep 'siblings'
[[Email protected] ~] # Arch# This is my R51 old notebook #
I686
[[Email protected] ~] # Cat/proc/cpuinfo # This is my R51 old notebook #
Processor: 0 # This indicates the first CPU kernel from 0 #
Vendor_id: genuineintel
CPU family: 6
Model: 13
Model name:Intel (
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