2014-10-21 Imagination Tech
MIPS is a shining star in high efficiency, low-power CPU design principles and has been in the mobile and embedded industries for nearly 30 years. This article will quickly explore the evolution of the MIPS architecture and describe how it evolved from the earliest version of Stanford University's Computational Science lab to the current architecture.
1. pipeline structure Pipeline-MIPs is one of the simplest architectures, so the university prefers to choose mips architecture to introduce the computing architecture course.-Arm has Barrel ShifterShifter has two sides. On the one hand, it can improve the speed of mathematical logic operations, and on the other hand, it also increases the complexity of hardware. Therefore, it is more efficient than adder/s
The ABI is the abbreviation for the application Binary interface, which identifies the operating mode of the processor and the encoding format of the specification target file.
The MIPS instruction set architecture formally supports the 64-bit mode of operation since MIPS3, so the code can follow O32 (o meaning old), N32 (n meaning new) and N64 Abi.
O32 and N64 are pure 32-bit and 64-bit modes, which, in addition to the length difference
Http://blog.163.com/tao198352__4232/blog/static/8502064520105984211236? Fromdm fromSearch isFromSearchEngine = yes
1. Pipeline StructurePipeline-MIPS is one of the simplest architectures, so the university prefers to choose MIPS architecture to introduce the computing architecture course.-ARM has barrel shifterShifter has two sides. On the one hand, it can improve the speed of mathematical logic operati
My colleagues who have developed Sigma smp8654 have noticed this. The following URLs of the MIPs GCC tool chain Used In SDK 3.11 are invalid.
Http://www.codesourcery.com/gnu_toolchains/mips/portal/package3546/public/mips-linux-gnu/mips-4.3-51-mips-linux-gnu-i686-pc-linux-gn
Build MIPS cross-compiling environment under Ubuntu
Cost Dickens, finally put MIPS cross compilation environment built. Next share this article with you, the method inside is I personally tried, absolutely easy to use. Thank you for the blogger who wrote this article.
MIPS is a RISC processor architecture, similar to the x86,arm and so on, today we introduce h
Add the following update source at the end of the/etc/apt/sources.list file:
Deb Http://ftp.de.debian.org/debian Squeeze MainDeb Http://www.emdebian.org/debian/squeeze Main
To perform a command installation:sudo apt-get updatesudo apt-get install emdebian-archive-keyringsudo apt-get install Linux-libc-dev-mips-crosssudo apt-get install Libc6-mips-cross Libc6-dev-mips
I will upload my new book "Write CPU by myself" (not published yet). Today is 13th articles. I try to write them every Thursday.
4.4 create the MIPs compiling environment
The openmips processor is designed to be compatible with the mips32 instruction set architecture. Therefore, you can use the existing GNU development tool chain under the mips32 architecture. This section describes how to install and use the GNU development tool chain and how to cre
After the system starts power-on, the default program entry of the MIPs processor is 0xbfc00000. The address is in the address area of kseg1 without caching, and the corresponding physical address is 0x1fc00000, that is, the CPU starts to get the first command from 0x1fc00000. This address has been determined as the flash location on the hardware. bootloader copies the Linux kernel image to a idle address in Ram, there is usually a memory movement ope
There's nothing wrong with configure.My configure is:./configure-prefix/opt/qt-jz-xplatform qws/linux-mips-g++-embedded MIPSConfigure passed, but when make, there was mips-linux-gcc:commond not fount!I'm MIPSL-LINUX-GCC, and I've cross-compiled a Hello world.The errors that occur when make are:MAKE[1]: Entering directory '/root/desktop/download/qt-jz/src/corelib 'mips
Thank you so much
http://blog.h5min.cn/ajianyingxiaoqinghan/article/details/70194392
http://blog.h5min.cn/zdyueguanyun/article/details/51322295
http://blog.csdn.net/tgww88/article/details/51393570
1, zlib of the cross-compilation:
./configure--prefix= $OPENCV _depend
1
1
After that, the makefile file is modified and the contents are as follows:
cc=mips-linux-gnu-gcc
Ldshared=mips-linux-gnu-gcc-s
1. Kernel stack Switching (MIPS)
When a dispatch switches to a process, the *KERNELSP is set based on the value of the task_struct->thread_info (the bottom of the kernel stack of the process currently running), and the value is Thread_info + thread_size-32 (MIPS, using SET_SAVED_SP macros).
2. Exception, interrupt register Save (MIPS)
When using Save_some to
Reprinted from http://blog.csdn.net/gujing001/article/details/8476685
MIPS Universal Register
MIPS has 32 general-purpose registers ($0-$31), the functions of each register and the use of the assembly procedures are as follows:
The following table describes the aliases and uses of 32 universal registers
REGISTER
NAME
USAGE
$
$zero
Constant 0 (constant value 0)
the process of writing and debugging. And because this part of the content is very stable, once successfully run, there is little need to modify. No need to change, who will go to see it. 2 context switching is a processor-related process, the so-called context is generally referred to as the CPU registers, and each processor register is different, the switching action is not the same, this article takes MIPS as an example to explain. 3 Embedded appl
The recent analysis of the implementation of Godson KVM, by the way and coarse look at the manual of MIPS, with the main KVM-related modules include: CPU Virtualization memory Virtualization of IO
The current godson on the CPU virtualization and the standard kernel difference is small, need hardware and software with support, the current godson overall can support. Kernel virtualization is the key to the Godson KVM scheme, which directly determines th
Stanford Algorithms (a): Multiply by large number (C + +)Just not in the Chinese university Mooc attended the course of Chen teacher 数据结构 , Harvest very big. Feel the strike, also put the algorithm part also to a school, on the Coursera registered a Stanford University algorithm class, the amount of the course is very heavy, estimated to learn a semester, slowly learn, steady.The course recommended a lot of books, I found a book, the title is called A
The instruction set can be divided into complex instruction set (CISC) and thin instruction set (RISC) two parts, representing the architecture are x86 (CISC),ARM and MIPS (RISC)respectively.arm- RISC is a chip system designed to improve processor speed, and its key technology is to complete multiple instructions in a single clock cycle. Compared with the complex instruction set CISC, the instruction set of the ARM instruction sets with RISC archite
1. QuestionsWhen reading or writing to a data unit using a fetch instruction under MIPS, the destination address must be an integer multiple of the number of bytes of data being accessed, which is called address alignment.For example, on the MIPS platform, when LH reads a half word, the memory address must be an integer multiple of 2; when LW reads a word, the address of the memory must be an integer multip
Rust application development in the OpenWrt router system of the MIPS platform, openwrtrust
Author: Liigo (Zhuang Xiaoli)
Date: January 1, September 17, 2014
Original: http://blog.csdn.net/liigo/article/details/39347541
Copyright, reproduced please indicate the source: http://blog.csdn.net/liigo
Target
Use the Rust language to develop application software on the MIPS (el) + OpenWrt router platform.
Compile
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