First, download the I2c-tools tool:Recently in the Transplant I2c-tools tool,: Https://i2c.wiki.kernel.org/index.php/I2C_Tools; Baidu to the git address in the wiki;1 git clone git://git.kernel.org/pub/scm/utils/i2c-tools/i2c-tools.git-b i2c-tools-3.1Download git to the ext
I2C has never been touched before, so its simulation function can only rely on the feeling, there is something wrong, still hope that the House correct. With the SPI-related simulation function, it is not difficult to do I2C, but it is a little troublesome for users to read and write data through the I2C bus.Test program running interface: the
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For more information about how to create i2c_client, see http://blog.csdn.net/yuanlulu/archive/2011/06/21/6557901.aspx.
2.6.34 I2C sub-systems no longer distinguish between legacy model and standard drivermodel drivers.
An in-depth understanding of I2C bus clock synchronization and bus arbitration
Each IIC bus device has the same circuit structure of the SDA and SCL pins, and the output drive of the pins is connected with the input buffer. The output is a field effect tube with an open drain path, and the input buffer is a high-input impedance phase generator [1]. This type of circuit has two features:
① Because SDA and SCL are Drain open circuit structures, the "lin
How to enable I2C device http://www.cnblogs.com/hangxin1940/archive/2013/04/02/2997077.html and build a python I2C Development Environment http://www.cnblogs.com/hangxin1940/archive/2013/04/03/2997094.html
Quick2wire is a python library used for I2C communication on Raspberry Pi. It allows non-root users to read and write gpio pins conveniently.
Why use it?
Some
The last 2 weeks have been debugging IIC and SPI bus equipment, here record 2 kinds of bus, in case of forgetting.
One IIC Bus
The abbreviation of I2c--inter-ic serial Bus is the serial transmission bus between chips introduced by Philips company. It implements duplex synchronous data transfer with 1 serial data cables (SDA) and 1 serial clock lines (SCL). The utility model has the advantages of less interface line, simpler control mode, smaller devic
I2C bus protocol
I2C bus protocol learning notes1. I2C ProtocolTwo two-way serial lines, one data line SDA, and one clock line SCL.The data transmitted by SDA is transmitted at a large end. Each transmission is 8 bits, that is, one byte.Multimastering is supported, and only one master can be created at any time point.Each device on the bus has its own AD
I2C transmits data between devices connected to the bus using only two wires (SDA and SCL. each device is identified by a unique address (whether it is a microprocessor, LCD driver, memory, or keyboard interface) and can be used as a sender or receiver based on the functions of the device. the LCD driver may be a receiver, while the memory can send and receive data. in addition to transmitters and receivers, the device can act as a host or slave when
with me, starting with a test without any knowledge, and then engaged in technology, and then became him 10 years later. I think I should be lucky to him. I just started technology after graduation, and now I am getting started, and I have been recognized by my colleagues and leaders. So I firmly believe that I don't need 10 years to achieve anything better than him. People are forced out. Only a firm belief will prompt us to grow and we will not be on the road to success. If you want or don't
I2C ProtocolTwo-line serial protocol (SCL, SDA), master-slave mode, support multiple master, but at the same time only one Master address composition: 7bit address array +1bit read-write bit, a total of 8bit. Address range 0~127, 0 address is broadcast address. Send 8bit data at a time, the data format is big-endian mode. Rate: Standard mode 100Kbps, fast mode 400Kbps, high speed mode 3.4Mbps.
Bus Interconnect
Note that both the SDA and the SCL requi
voltage is the local voltage ), the high level indicates 1 (the voltage is determined by the VDD of the component ). The SDA level can be changed only when the SCL line is low.5. Response Signal ACKThe I2C bus data is transmitted in bytes (8 bits). After each byte is sent, the device releases the data bus during the 9th pulses of the clock, the receiver sends an ACK (which lowers the power of the Data Bus) to indicate that the data is successfully re
/********************************************************************** * Linux tmp75/dev/i2c-* get Data demo * Description: * Previous attempts to read the EEPROM in this way, the result failed, and did not find the reason, * today, the problem is fixed due to i2c_slave, I2c_slave_force caused by the previous attempt * i2c_slave, today to locate the problem is the I²C bus Busy, change to use I2c_slave_force to solve. * There is the test procedure, un
About I2C, this is also the previously tangled part. Note.
(For details, refer to: source; Phodal'sBlog)
The I2C (Inter-Integrated Circuit) bus is a two-line serial bus developed by PHILIPS to connect the microcontroller and its peripheral devices. It is a bus standard widely used in the field of microelectronics communication control. > The I2C bus supports any
that I could. But the expansion of G is really a little slow. It takes about 10g a minute. But fortunately, I finally finished it, and made a sweat.
In the afternoon, I checked the setting of Interrupt registers on 8607. Use three interrupt registers, 0x [3-5], and each bit uses a mask to set an interrupt. Every one is 8 bits. There are also 24 interruptions. This is read and write using I2C. I was a bit confused when I was writing registers. When I
# Modify the configuration file
Raspberry Pi has integrated the I2C driver and only needs to be started.
Modify configuration file
Sudo nano/etc/modprobe. d/raspi-blacklist.conf
! [Configure] (http://images.cnblogs.com/cnblogs_com/hangxin1940/466697/o_rasp_i2c1.png "comment the third line ")Comment out the third line, CTRL + x save
Next, start the I2C module.
Sudo nano/etc/modules
! [Configure] (ht
According to their own understanding, the http://lxr.linux.no/linux+v2.6.34/Documentation/i2c/instantiating-devices is translated into the document about enumerating and establishing i2c_client. Have objections or questions please refer to the original, after all, the core of the document is the true essence.
Method 1: Use the bus number to declare the device. defines the device's information in the initialization of the kernel. The prerequisite is
AbstractFm31256 is a multi-functional storage chip based on I2C bus and powered by the iron and electronics technology. In addition to non-volatile memory, the device also provides real-time clock, low-voltage reset, watchdog counters, non-volatile event counters, lockable serial digital identification, and other features. This article mainly introduces the basic functions and principles of fm31256, and gives the specific application methods of fm3125
Addressing of Bus
(1) Definition of addressing byte
I2C bus uses 7-bit addressing bytes, which are the first byte after the starting signal.
D7 ~ The address of the slave machine composed of D1 bits. D0 is the data transmission direction. If it is set to "0", it indicates that the host writes data to the slave database. If it is set to "1", it indicates that the Host reads data from the slave database.
(2) AddressingWhen the host sends the addre
The driver is suitable for all Ferroelectric series I2C Fram, only the capacity, level (3V and 5V), the driver is for 51MCU, but only slightly modified for other MCU can be used.
When the amount of storage data is small and the frequency of reading and writing is frequent, I2C FRAM can be selected.
This CODE is designed to demonstrate how the fm24c04/fm24c04a serial FRAM couldBe interfaced to the 8051 micro
Linux under a lot of devices are used to the I2C, so look at the driver of the I2C, although now understanding may still be human and material resources, but at least there are some basic concepts
Reference:
http://blog.csdn.net/ylyuanlu/article/details/6705942
http://blog.csdn.net/hongjiujing/article/details/4098547
Look at the I2C initialization process:
[CP
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