Each PLL has three global clock networks, but one of them (C3) can also be used as an external clock (at the same time)
Does it mean that C0 C1 can only be used as a global clock, but not an external clock ??? The actual test can be used as an external tell me why?
(1) After reading so many calls, I still don't understand the concept of resetting the clock pin, what is the global clock, and clk0 ~ What is clk7 ???
(2) General
The PLL is actually a negative feedback system that synchronizes the clock on the circuit with the phase of an external clock
The PLL phase-locked loop has three components:Phase detector PD, loop filter lf and voltage controlled oscillator VCO
Principle:
The external input reference signal is used to control the frequency and phase of the internal oscillation signal in the loop.PD, which detects
PLL and CLK Classification
By default, the operating frequency of the S3C2410 CPU is 12 MHz. The PLL circuit can generate a higher clock speed for the CPU and peripheral devices.
The S3C2410 has two PLL: MPLL and UPLL, which are dedicated to UPLL and USB devices. MPLL is used for CPU and other peripheral devices.
MPLL generates three clock frequencies: FCLK, HCLK
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