--verilog synthesis and simulator for the design of the Ming de Yang to the simple method

VERILG is the hardware description language, as the name implies, is to describe the function of the hardware in the form of code. And we are finally going to implement this on the circuit. When Verilog describes the hardware function, we need the synthesis to interpret the Verilog code, translate the code into the actual circuit to represent it, and ultimately the actual circuit, which we call the grid table. This tool, which turns Verilog code into a web-meter, is the integrated device. The upper-left corner is a copy of the Verilog code that describes an adder function. After the code has been interpreted by the synthesis, it is converted into an adder circuit. QUARTUS, Ise, and Vivado are all integrated, and ICS are commonly used as a DC.

In the FPGA design process, there will inevitably be a variety of bugs. If we write code, integrated into the circuit, burned to the FPGA, only to see the problem, at this time to locate the problem will be very difficult. Before the synthesis, we can test the code in the computer simulation, the bug found to solve, and finally burned into the FPGA. We can assume that there is a bug in the code that is not validated by the simulation.

In order to simulate the real situation, we need to write a test file. The file is also written in Verilog, which describes the input excitation of the simulation object. The incentive attempts to imitate the most real situation, generate the most near the excitation signal, the waveform of the signal input to the simulation object, to see whether the output of the simulation object is consistent with the expected.

To do the simulation verification, we wrote the test file. Add the test file and the tested object to the emulator. The emulator interprets the test file and the code of the object being tested. According to the test file, generate test excitation, input to the tested object, and according to the code of the complement test object, produce the output of the object being tested. It is important to note that during the simulation, the code is not turned into a circuit, and the emulator simply validates the code. As to whether the circuit can be turned into a circuit, the emulator is not concerned.

Common emulators are Modelsim and VCs.

Thus, the Verilog code can not only describe the circuit, but also can be used for testing. In fact, Verilog defines a lot of syntax, but most of it is used for simulation testing. Only a small part is used in the circuit design, in detail can refer to the book "Integrated Logic Design" section.

Verilog in the design of the grammar, is the focus of learning. Mastering the grammar of design, proficiency in a variety of complex projects, this is the core of skills. The syntax for other tests is sufficient to find and reference when needed.

This book focuses on the use of undergraduate and postgraduate teaching, so it will focus on the design grammar.

When explaining VERILG in this chapter, the purpose of the grammar is explained from the perspective of the synthesis and emulator, and the reader can understand the key things to learn.

--verilog synthesis and simulator for the design of the Ming de Yang to the simple method