0K6410 learning Uboot_stage1

I have a lot of water to drink today. As I said, I have no room to read for three days, and I have done a good job. Indeed, there seems to be nothing worth my attention in the space. Well, just roughly the u-boot-2010.03 inside the arm11 source code looked at, I use arm11 Board, which has some is reference to the analysis of the arm9's data, after the analysis, I still think it is necessary to summarize it, in case I forget it. Okay, let's get started with stag1.

Disclaimer: I may have misunderstood some of the content for your reference only. You are welcome to join us.

I,Open cpu/arm1176/start. S. This file is the first code executed after the system is powered on, but it is not the first code executed by the compiler. I believe it is clear. Starting from start. s, there is nothing to say about the header file, and the next step is:

.globl _start_start:b       reset

. Globl defines a global variable that can be referenced by other documents. This is the entrance of the entire uboot program, which can be found in the Link script board/S3C2410/u-boot.lds, the link script defines the entry address of this program, this command indicates that the board is reset as soon as it comes up ~~~

II,This module is divided into the exception handling vector table of the processor. The address range is 0x0000 0000 ~ 0x0000 0020, 8 commands

#ifndef CONFIG_NAND_SPLldrpc, _undefined_instructionldrpc, _software_interruptldrpc, _prefetch_abortldrpc, _data_abortldrpc, _not_usedldrpc, _irqldrpc, _fiq_undefined_instruction:.word undefined_instruction_software_interrupt:.word software_interrupt_prefetch_abort:.word prefetch_abort_data_abort:.word data_abort_not_used:.word not_used_irq:.word irq_fiq:.word fiq_pad:.word 0x12345678 /* now 16*4=64 */#else. = _start + 64#endif.global _end_vect_end_vect:.balignl 16,0xdeadbeef

The. Word pseudo operation is used to allocate a segment of memory units (the allocated units are word-aligned) and initialize with exceptions .. The principle of Long is the same as that of. Int .. The balign pseudo operation is used to indicate alignment. By adding the padding byte, the current position can meet certain alignment conditions .. The detailed usage of balign is Baidu.

If the system encounters an interrupt exception, the following code will be executed. The code is still in start. S.

/** Exception handlers */. align 5undefined_instruction: commandid: get_bad_stackbad_save_user_regsbl handle: includo_not_used # ifdef CONFIG_USE_IRQ.align5irq: commandid: get_fiq_stack/* someone ought to write a more effiction fiq_save_user_regs */irq_save_user_regsbl do_fiqirq_restore_user_regs # else. align5irq: get_bad_stackbad_save_user_regsbl do_irq.align5fiq: get_bad_stackbad_save_user_regsbl do_fiq # endif

III,The next step is to declare and initialize some variables.

1. TEXT_BASE is defined in the config. mk document in the directory related to the R & D board. It defines the address of the code at runtime and saves the address in _ TEXT_BASE.

_TEXT_BASE: .word TEXT_BASE 

2. The following Code declares _ armboot_start and uses _ start for initialization, which is defined in the board/u-boot.lds.

.globl _armboot_start _armboot_start: .word _start  

3,

1. The following Code declares that _ bss_start is initialized with _ bss_start, where _ bss_start is defined in the board-related u-boot.lds, _ bss_start

1. _ bss_start stores the address of the _ bss_start label. Here, the address of the current code is not the address at compilation. Here, the address corresponding to the label is obtained directly,
Not compiled

Address impact.

.globl _bss_start _bss_start: .globl _bss_start _bss_start: .word __bss_start 

3. The same is true for _ bss_end.

.word __bss_start .globl _bss_end _bss_end: .word _end

1. OK. Check the reset function. No, it should be called the reset code!

/* * the actual reset code */reset:/* * set the cpu to SVC32 mode */mrsr0, cpsrbicr0, r0, #0x3forrr0, r0, #0xd3msrcpsr, r0

/* First set the CPU to the management mode we are familiar with (by setting the lower 5 bits of CPSR to 10011 ). IRQ and FIQ are also prohibited. That is, the seventh and sixth digits of CPSR are set to 11, which is explained in the previous blog on interruption.

1. Disable cache and MMU. Why? It is said that if you only press the reset key and do not turn off the board and power it on again, it may cause the cache to retain the data previously operated on the cache. We call it "dirty data", which will mirror our debugging results and create an illusion. (A Chance To try)

Of course, there must be other reasons for invalid cache and MMU. For example, in the initialization phase,

We can think that we only have one task to run. It is unnecessary and cannot use address translation. Therefore, it is best to disable MMU. (Refer to arm79)

#ifndef CONFIG_NAND_SPL/* * flush v4 I/D caches */movr0, #0mcrp15, 0, r0, c7, c7, 0/* flush v3/v4 cache */mcrp15, 0, r0, c8, c7, 0/* flush v4 TLB *//* * disable MMU stuff and caches */mrcp15, 0, r0, c1, c0, 0bicr0, r0, #0x00002300@ clear bits 13, 9:8 (--V- --RS)bicr0, r0, #0x00000087@ clear bits 7, 2:0 (B--- -CAM)orrr0, r0, #0x00000002@ set bit 2 (A) Alignorrr0, r0, #0x00001000@ set bit 12 (I) I-Cache/* Prepare to disable the MMU */#if 0adrr1, mmu_disable_phys/* We presume we're within the first 1024 bytes */andr1, r1, #0x3fcldrr2, _TEXT_PHY_BASEldrr3, =0xfff00000andr2, r2, r3orrr2, r2, r1bmmu_disable.align 5/* Run in a single cache-line */mmu_disable:mcrp15, 0, r0, c1, c0, 0nopnopmovpc, r2#endif#endif

1. Call the lowlevel_init underlying initialization function. Initialize PLL, initialize MUX, and disable memory. (This should be carefully analyzed against the chip Manual ).

 

2. After the code is copied, MMU can be enabled.

#ifdef CONFIG_ENABLE_MMUenable_mmu:/* enable domain access */ldrr5, =0x0000ffffmcrp15, 0, r5, c3, c0, 0/* load domain access register *//* Set the TTB register */ldrr0, _mmu_table_baseldrr1, =CONFIG_SYS_PHY_UBOOT_BASEldrr2, =0xfff00000bicr0, r0, r2orrr1, r0, r1mcrp15, 0, r1, c2, c0, 0/* Enable the MMU */mrcp15, 0, r0, c1, c0, 0orrr0, r0, #1/* Set CR_M to enable MMU *//* Prepare to enable the MMU */adrr1, skip_hw_initandr1, r1, #0x3fcldrr2, _TEXT_BASEldrr3, =0xfff00000andr2, r2, r3orrr2, r2, r1bmmu_enable.align 5/* Run in a single cache-line */mmu_enable:mcrp15, 0, r0, c1, c0, 0nopnopmovpc, r2#endif

1. Clear the heap and set the stack. Why? Call the C function.

skip_hw_init:/* Set up the stack*/stack_setup:ldrr0, =CONFIG_SYS_UBOOT_BASE/* base of copy in DRAM*/subr0, r0, #CONFIG_SYS_MALLOC_LEN/* malloc area*/subr0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo*/subsp, r0, #12/* leave 3 words for abort-stack*/clear_bss:ldrr0, _bss_start/* find start of bss segment*/ldrr1, _bss_end/* stop here*/mov r2, #0/* clear*/clbss_l:strr2, [r0]/* clear loop... */addr0, r0, #4cmpr0, r1bleclbss_l

1. After the CPU Initialization is complete, you can see such a piece of code.

#ifndef CONFIG_NAND_SPLldrpc, _start_armboot_start_armboot:.word start_armboot#elsebnand_boot/*.word nand_boot*/#endif#ifdef CONFIG_ENABLE_MMU_mmu_table_base:.word mmu_table#endif#ifndef CONFIG_NAND_SPL 

Obviously, we didn't copy the code here, so we went directly to the C function, _ start_armboot.

Call the first C function and start to enter the C world. uboot starts Stage 2!

Jump to the start_armboot function entry. _ start_armboot indicates the function entry pointer.

The start_armboot function is implemented in lib_arm/board. C.

 

After summing up stage1, it's almost time to go to bed. To be continued, stage2 ....