1-4 simplified model of computer architecture

A simplified model of computer structure (model machine)

1. The model machine contains two parts of CPU and memory, the middle is connected by the system bus

2. The system bus is also subdivided into three parts of the control bus, address bus and data bus

3.CPU and memory (memory, not hard disk) each has its own corresponding structure

Second, first look at the memory (ie memory)

1. The bit width of the storage unit is determined by the memory addressing method when the computer is designed.

If memory is addressable by byte, each storage unit can hold 8-bit binary number

2. The address of the storage unit is unique, and the addresses of different storage units differ.

To access a storage unit, the CPU must give the corresponding address via address bus

3. If the width of the address bus is N, the CPU can manage a maximum of 2^n storage units,

such as n=32, can access 2^NB = 4G

4. The memory contains Mar:

<1>mar,memory address register, memory address register, for storing the addresses of the storage units that the CPU is reading or writing (the address is stored)

5.CPU data to be read and written is transmitted via the data bus, the width of which is generally the integer multiple of the storage unit's bit width.

6. The corresponding data will be present in the MDR:

Mdr:memory data Register to hold the CPU reading or writing to the storage unit (data is stored)

7. Finally, the control bus is connected to the control logic in the memory to receive read-write signals from the CPU or transmit the completed signals to the CPU feedback.

8. Baidu: The main memory data register (MDR) in the computer and the memory address register (MAR) Help to complete the communication between the CPU and the primary storage,

Mar is used to hold the address that the data is transferred to or the address of the data source.

MDR saves data from an address unit to be written to or read from an address unit

9. The following is the principle of computer composition-Tangshaofei-Explanation of Mar and MDR in the second edition:

To enable access by address, two registers Mar and MDR must also be configured in main memory,

Mar is a storage address register that holds the address of the storage unit you want to access, the number of bits corresponding to the number of storage units,

(If the Mar is 10, then there is a 2^10=1024 memory unit, recorded as 1K).

A MDR is a stored data register used to store code taken from a cell in a storage unit or to be sent to a storage unit for deposit.

The number of digits and the storage word looks and so on.

Of course, in order to complete a take or save operation, the CPU also has to give main memory a variety of control signals, such as read commands, write commands, and address decoding drive signals.

With the development of hardware technology, main memory is made of LSI chips, and the Mar and MDR are integrated into the CPU chip

Thirdly, the controller of the CPU of the model machine

1. The controller is used to control the various parts of the computer to complete the command, analysis instructions and execution instructions and other functions, the main components are as follows:

<1> instruction Register, ir,instruction register

Used to store an instruction that is executing or is about to execute, which is taken from memory and stored temporarily in this register.

<2> program counter, Pc,program Counter

The address of the storage unit for the next instruction, with the ability to automatically increment the count

<3> memory address registers, Mar,memory addresses

The address that the MAR uses to hold the storage unit at the time of the visit

<4> Memory Data Register, Mdr,memory

MDR is used to store data read/write to the storage unit at the time of the visit

<5> Instruction decoding Parts

The instructions in IR are decoded to determine which instruction is stored in the IR

<6> control circuit

After the instruction is determined, the control circuit generates a control signal to control the action of each part in the synchronization of the timing pulses.

Four, the CPU of the model machine computing device

Not to be continued ...

　　　　　　

1-4 simplified model of computer architecture