10.6 Direct Memory Access mode

Computer composition 10 Input 10.6 Direct Memory access mode

Let's just say The courier. One day, you sit in this operation, suddenly call, then you take a listen, ah, there are courier, ah what? 1000 books, now you have to take, oh, good. What about this? Well, that's a lot of time to move 1000 books, and, uh, to do that, we'll call a moving company, tell them where we're going to move to, talk about the price, they move, and tell them to give me a call when they're done, and then I'll check it out. Well, it would be worthwhile to spend more money, but it would be worth it if you could do more important tasks.

That's the way we're going to say DMA.

Today's computers have many complex peripherals such as monitors, networks, and hard drives. These peripherals need to transmit a large amount of data, and the rate of transmission is also very high requirements, if the data is to rely on the CPU one by one to carry, it is probably difficult to deal with.

Therefore, this requires the use of the DMA IO control mode.

DMA is the abbreviation for Direct memory access. If the DMA mode of I/O data transmission in the process is not CPU intervention, the work of the data transfer is a specialized hardware circuit control, you can directly transfer peripheral data to the memory or memory data to the peripherals, This specialized hardware control circuit is called the DMA controller, referred to as DMAC. In fact, the DMA controller itself is an I/O interface, similar to other I/O interfaces, it was early in the form of independent chips, and now is usually integrated into other multi-functional chips.

Let's look at the basic working steps of the DMA controller. This is a simplified system with a CPU, a memory, an I/O interface, and a DMA controller, which are connected through the system bus. Both M and s are added, and M is the abbreviation for master, which indicates that the component can initiate transmission on the system bus. For example, the CPU is such a component, it can actively initiate read and write transmission on the system bus. S is an abbreviation for slave, which indicates that the part can only passively accept transmissions from the system bus. Memory is a typical device that only has a slave interface. The general I/O interface is also the case and only accepts access from the CPU. The DMA controller has both a master interface and a slave interface.

Then we will use this DMA controller to carry out a peripheral to the memory transfer, we can think of this I/O interface is a network card, outside the network cable. Now we need to receive a network packet in DMA mode and save it to an area of memory. To do this, the CPU first needs to set the configuration register inside the DMA, and for X86CPU, we need to write some I/O ports (yellow arrows) in the DMA controller with out instructions to configure its operating mode. The DMA controller is then idle, and the CPU can perform other programs. When the peripheral sends the data to the I/O interface, the I/O interface sends a DMA transfer request to the DMA controller, which needs to be emitted via an additional connection (purple arrow), and the DMA controller receives an I/O interface request, and responds to the request via another connection (purple arrow). The DMA controller then initiates a bus-read transmission through its master interface, which is the data-entry buffer register in the I/O interface. The data will be read from the I/O interface to the DMA controller (light blue tip), then the DMA controllers will initiate a write transfer to the memory bus, and write the data just read back to an area of the memory (light blue tip). We note that only the CPU in this system can initiate bus transmissions before the DMA controller is available, and now the DMA controller can initiate the bus transfer proactively. Then the DMA controller repeats five and six of these two actions, continuously reading the data from the I/O interface and then writing to the memory. If this is the network transmission until a network packet is received, this time the DMA transfer is completed, and then the DMA controller returns to the second step, waiting for I/O to initiate the next DMA transfer request.

There can be a lot of data at a time, and it takes a long time, but during this time the CPU is able to perform other programs, which in parallel with the data transfer can achieve good system performance. But how does the CPU know that the DMA transfer is complete? Typically, when the DMA transfer is complete, the DMA controller sends out an interrupt request signal, notifying the CPU by interrupting the controller. The interrupt from this DMA controller is also an external interrupt, and the subsequent processing is the same as the interrupts from the other I/O interfaces, except that the interrupt service program is for the CPU to process the DMA transfer. So, from this step we can see that the DMA mode is not completely without CPU intervention. The CPU is configured when the DMA is started, and the CPU needs to be processed after the transfer is complete. The subsequent processing varies according to the needs of the task, while the initial configuration is roughly the same.

Before the DMA transfer begins, the CPU will set the registers inside the DMA controller, which is usually set at least. Since the DMA controller is going to transfer data, it needs to be set up where to start, which is the initial value of the source address. You also need to set whether the source address is incremented or decremented during the transfer process. You will then need to set up where these data transfers are, that is, the initial value of the destination address and how the address is added or decreased. Finally, you need to set how much data to transfer. So let's take the example of the peripheral-to-memory transmission we just mentioned.

When the CPU initializes the configuration, a source address is set to the I/O port. For example, a network controller's data input register port, and the transmission of this source address is unchanged. Because each time the DMA controller reads data from the same I/O port, the destination address is set to an address of the memory, and the address is incremented at the time of transmission. In this way, the DMA controller reads a number from the I/O interface and writes the number to the memory, and the address should increment the next time it reads a number and then writes it to the memory. This will not overwrite the number just passed over. The third is to set the length of the data to be transmitted. If the data is received from the peripheral, the CPU may not know how long the data is in the configuration, it can not set this parameter, and finally according to the I/O interface control signal to determine whether the transmission is complete, if it is to send a set of data from the memory to the I/O interface, At this point, when the CPU is initialized to know exactly how long to send the data, you need to set this parameter to the length of the data to be transmitted. It should be emphasized that these parameters are internal registers of the DMA controller, generally each has an I/O port address, programmed with out instructions to the CPU to write these I/O ports, so that the source address, destination address and the length of the data to be transmitted, etc. The DMA controller does not need to rely on the CPU execution program to control, but directly view the internal source address register, send the corresponding address to the system bus, read back the corresponding data from the I/O interface, and then view the destination address register, This address is sent to the system bus along with the data just read, so it is written to the memory. For each read and write, the length of the transmitted data is accumulated internally, and compared to the contents of the register of the length of the data to be transmitted, if the equivalence means that the transmission has been completed, and if not equal, continue the transmission. Therefore, after the CPU is configured at once, the subsequent work is done automatically by the DMA controller's internal hardware, eliminating the need for CPU intervention. This is the meaning of the so-called direct memory access.

There is no DMA controller in the earliest personal computer, and later in order to improve the efficiency of the input and output, the independent DMA controller is added to the chip. For example, just mentioned in 8237, the CPU set the DMA controller in the different addresses can be used for different I/O interface to provide DMA services.

However, with the development of computer, some I/O interfaces are more and more fast, and the requirements for DMA transmission are more and more high. The way multiple I/O interfaces share a separate DMA controller may not be able to meet the needs of some I/O interfaces.

The I/O interface with the DMA controller is present and the I/O interface has a dedicated DMA controller that serves only this I/O interface, which now has the Master bus interface. In the video card, network card, hard disk controller, these to the transfer rate of high-demand I/O interface will generally be self-contained DMA controller. When the system is initialized, the CPU has to configure each DMA controller, and then the external transmission requirements, these DMA controllers can automatically start to work. If we compare the independent DMA controller on the left to a moving company, the CPU will ask the moving company to complete the data handling between the I/O interface and the memory. In some departments, the handling workload is very large, actually need a moving company to serve them all the time to meet the demand. So in the department to set up their own a transport team, so that once the need for data transmission can be started immediately, without the need to apply for external DMA controller, the efficiency of the transmission will be greatly improved, and different I/O interfaces have different transmission characteristics. For example, the behavior of display, network, hard drive transmission must have different characteristics, and the embedded DMA controller can be customized according to the characteristics of I/O interface, so as to complete the transmission more efficiently.

In modern computing systems, most of the devices with higher data rates require a DMA controller, while other devices with lower data rates require a separate DMA controller in the system. In addition, this standalone DMA controller generally provides services from memory to memory transfer, while we are programming a large chunk of data in memory to another area of memory, although not involving input and output, but also can enjoy the benefits of DMA.

And of course not all input need to use DMA. After all, adding a DMA controller requires increasing the cost of manufacturing, and it takes time for the CPU to configure the DMA controller and to perform subsequent processing or execution of the program. If the amount of data to be transferred is small, performance will become worse.

Those devices that use DMA now are not necessarily the work CPUs that are unwilling to do so, and may not be able to do it at all.

For example, we express to send not 1000 books but 10,000 books, and must finish within one hours. So you could do it? We have to call the movers, right? But it doesn't mean that everything can be solved in a DMA way. For example, not 1000 of the 10,000 books, but a book, then you also go to a moving company to bring this book to you? That is not worth the candle, and sometimes you may send it is not a book at all, but your lunch. Ordered a bento, do you also call a moving company to collect this lunch box for you? It may be two hours before they come, and then use their canonical method to send you this meal to their big truck in the box. And then shipped to your downstairs, and then unpacking, and then sent to you, can catch up with dinner is good.

10.6 Direct Memory Access mode