The integrated image processing hardware platform includes 2 blocks of image signal Processing Board, 1 blocks of video processing board, 1 blocks of main control Board, 1 blocks of power Plate, and 1 blocks of VPX backplane. First, the Board of Cards overview The image signal Processing board includes 2-piece TI multicore DSP processor-tms320c6678,1 Chip Xilinx FPGA xc7k420t-1ffg1156,1 chip Xilinx FPGA xc3s200an. Achieve quad Gigabit Ethernet output with two 422 outputs. Through the GTX of the FPGA, Lvds realizes high-speed backplane interconnection. The 6u VPX architecture is used. The chip meets the industrial level requirements, the Board meets the seismic requirements.
The video signal processing board loads the video signal for processing, return or output. The board features a dual TI 8-core DSP processor Tmsc6678,xilinx k7-xc7k420t processor, Xilinx's Spartans Xc3s200an processor, and TI's MSP430 processor. Which CFPGA is responsible for the management of board power sequencing, clock configuration, System and module Reset, MCU is responsible for detecting the board temperature, power supply.
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two, technical indicators
Support 2 tms320c6678 chip, each DSP external ddr3,256m x 64bit capacity, Nor Flash 16M x16bit capacity, 4 channel Ethernet interface, DSP through hyperlink x4 Interconnect, support 4 x 3.125Gbps bandwidth. The DSP and K7 directly interconnect via the RapidIO x4 mode, supporting 4 x 3.125 GBP speed, The DSP and the K7 are interconnected via the I2c,spi,uart,gpio interface. DSP Debugging for ordinary Jtag port, Fpga-k7 for BPI mode. The board requires an industrial grade chip. The structure meets the seismic requirements. The board uses dual power supply, 12v~6a,5v~1a.
three , interface interconnect design
Two pieces of 6678 connected via Hyperlink x4 @3.125gbps/per Lane. Each 6678 SGMII-0 is connected to the pin via a PHY chip. Each of the 6678 SGMII-1 is connected to the VPX-P4 via the PHY chip. Each 6678 PCIe x2 is connected to the VPX-P3. Each piece 6678 and K7 via SRIO x4 @ 3.125G bps/per Lnae interconnect. Each piece 6678 and K7 realizes Gpio,spi,i2c,uart interconnection. Each piece 6678 and CFPGA realizes Gpio,spi interconnection. K7 and CFPGA implement GPIO interconnect. The K7 GTX x20 is connected to the VPX P1,P2,P3 interface respectively. The K7 LVDS x10 is connected to the VPX-P5. The K7 outputs two sets of 422 signals connected to the VPX-P4. 4
Four , software code
DDR3 read-write test test Norflash Software read/write test Nandflash Software read/write test EEPROM read/write Test Gigabit Ethernet test, support UDP transport protocol Hyperlink interconnection Test Norflash Program Load Test K7 DDR3 Software Read-write test K7 BPI Program Load test K7 SPI Norflash Read-write test Dspa/b and K7 i²c interconnect test Dspa/b and K7 SPI interconnect test Dspa/b and K7 GPIO interconnect test Dspa/b and K7 UART interconnect test Dspa/b and K7 SRIO interconnection test
Five , physical properties:
Size: 6U VPX board, size is 160x233.35mm.
Operating temperature: 0℃~ +55℃, support industrial grade -40℃~ +85℃
Operating Humidity: 10%~80% Vi.. System Construction:
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Click here to learn Vii. Fields of Application
Software radio system, baseband signal processing, wireless simulation platform, high-speed image acquisition, processing and so on. |
