20145239 "Information Security system Design Fundamentals" 7th Week Study Summary

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20145239 "Information Security system Design Fundamentals" The 7th Week study summary textbook Learning content Summary

6.1 Storage Technology

6.1.1 Random access memory (divided into two categories)

Static RAM (SRAM): Fast, as cache memory. (hundreds of thousands of MB)

Dynamic RAM (DRAM): As main memory, the frame buffer of the graphics system. (<= a few megabytes)

1. static RAM

With a dual stable state , it can be kept for a period of two different voltage configurations (states) one of them. can also be kept in a sub-stable state, but this state is susceptible to interference. Because of its dual stability, even if there is interference, when the interference is eliminated, it can be quickly restored to a stable value.

2. Dynamic RAM

DRAM stores each bit as a charge to a capacitor. Sensitive to interference, the voltage of the capacitor will never recover after being disturbed.

3. Traditional DRAM

The DRAM chips are divided into D-units, each with a W-bit. A i,j is used to represent a super-unit. The chip is connected to the storage controller circuit and can be outgoing (into) W bits at a time (that is, the contents of a single cell). The first outgoing I (RAS) copies all the cells of the line I to the internal buffer, and then the column address J (CAS) sends the (I,J) Hyper-unit. The design of the two-dimensional array reduces the number of pin address bits, but the two-step sending address increases the access time.

4. Memory Module

The DRAM chip is packaged in a memory module and the memory module is plugged into the expansion slot of the motherboard. Common types: Dual-inline memory modules (168-pin, 64-bit block), single-line memory module (72-pin, 32-bit block). Multiple memory modules are connected to the storage controller to aggregate main memory.

5. Enhanced DRAM

    • Fast-page Mode dram
    • Expand Output DRAM
    • Synchronous DRAM
    • Double Data rate synchronous DRAM
    • Rambus DRAM
    • Video dram

6. Non-volatile memory

(Sram,dram are volatile memory.) )

Non-volatile: no loss of information after power failure.

ROM: Read-only storage (read-only memory) It has a type that can read and write as well as historical reasons to call it.

ROM classification: (based on the number of times that can be reprogrammed, written, and the mechanism used for programming)

PROM: can only be programmed once.

Erasable programmable ROM (EPROM): Programmed 105 times

Flash: Based on EEPROM, provides fast and durable nonvolatile storage for a large number of electronic devices.

Firmware: A program stored in a ROM device.

7. Accessing main memory

A bus is a set of parallel conductors that can carry addresses, data, and control signals.

Data transfer between CPU and main memory: the shared electronic circuit of the bus is round-trip to the processor and DRAM main memory.

Bus transaction: Read transaction (main memory transmits data to CPU , that is, the CPU read from main memory), write transactions (CPU transfer to main memory)

A typical bus structure that connects CPU and main memory:

CPU Chip

I/O Bridge chipset: Storage Controller

DRAM memory module for main memory

System bus: Connecting CPU and I/O bridge

Memory bus: I/O bridge connected to main memory

Two examples: Movl a,%eax; and MOVL%eax,a;

Example 1

Example 2

6.1.2 Disk storage

Big, but slow. DRAM is 100,000 times times faster and SRAM is 1 million times times faster.

1. Disk Construction

A disk (spinning disk) consists of one or more platters stacked together and encapsulated in a fixed container. The platter has two surfaces with a rotating spindle at the center of the platter, with a fixed speed of 5400~15000 to every minute. The entire device is called a disk drive.

Track: A surface spreads from the center of a circle, dividing a set of concentric circles.

Sectors: Stores the number of data bits.

Gap: Stores the formatted bits of the identity sector.

Cylinder: A collection of tracks with a radius equal to the distance.

2. Disk Capacity

Disk capacity: Maximum disk capacity.

Disk capacity = number of bytes per sector * average number of sectors per track * number of tracks per surface * number of surfaces per disc * total disk face number of disks

(Note: Dram,sram Capacity: k=210,m=220,g=230,t=240

However, the capacity of the disk, I/O device: k=103,,m=106,g=109,t=1012. But it's nice to note that the corresponding values are relatively low. )

3. disk Operation

Seek time: The time the read and write head is positioned on the track. Usually: 3~9ms

Rotation time: The time to the track, waiting for the target sector. Maximum rotation delay:

Tmax rotation=1/rpm * 60secs/1min

average rotation time (delay): the largest half.

Transfer time: The time it takes the drive to read and write content.

tavg Transfer=tmax Rotation * 1/ average number of sectors per track

Summary of calculations:

time is mainly spent on seek and rotational delays.

seek time and rotational delay are roughly equal, the general direct seek time.

Logical Disk BLOCK:

Disk controller: Maintains a mapping relationship between logical block numbers and physical disk sectors. (read disk sector data to main memory, disk controller will execute a quick lookup table, the logical block number is translated into a disk, track, sector of the ternary group.) )

4. Connecting to I/O devices

Universal Serial Bus (USB)

Graphics Card (Adapter)

Host Bus Adapter

5. Accessing the disk

CPU reads data from disk:

    1. CPU sends command, logical block number, destination storage address to disk controller
    2. The disk uploads the CPU's required content to main memory (called DMA transfer)
    3. After the DMA is transmitted, the disk sends an interrupt signal to notify the CPU that it has passed.

6. Analysis of commercial disks

Dixtrac can automatically discover a lot of low-level information about SICI disk construction and performance.

6.2 locality of

locality principle: Programs tend to refer to data items that have been recently referenced or are data items themselves.

Time locality: The memory location is referenced multiple times.

Spatial locality: the location near the memory location is referenced in the not too distant future.

6.2.1 locality of reference to program data

The reference pattern for a step is a sequential reference pattern. Every k-element is accessed, referred to as a reference pattern with a step of K.

6.2.2 locality of the instruction

The circulation body has good time and space locality

6.2.3 Summary of Local laws

A program that repeatedly references the same variable has good time locality

for a step of K the reference mode, K the smaller the space, the better the spatial locality.

for the fetch instruction, the loop has good time and space locality. The smaller the loop body, the more the loop iteration number, the better the locality.

6.3 Memory Hierarchy

6.3.1 caching in the memory hierarchy

cache: The buffer area of the next layer (a larger and slower device for itself) . The process of using cache is called caching.

The central idea of the memory Architecture hierarchy: Each layer in the hierarchy caches data objects from the lower rub.

Blocks: Each layer is divided into contiguous pieces of data objects. The size of the block can be fixed or variable in size. Data is always in blocks as a transfer unit. The block size of the neighboring levels is the same, and the others can be different. (Example: L0,l1 uses a block of 1 words, L1,L2 uses 8~16 blocks).

1. Cache Hits

The program requires the data Object D of the k+1 layer, and D is just in a block of the K layer.

2. Cache Misses

Is the opposite of cache hits.

3. Types of cache misses

Mandatory miss (cold not hit): The last layer of cache is empty resulting in a miss.

Placement Policy:

High-level cache (near CPU) for expensive versions:

Allows any block of the k+1 layer to be placed in any block of the K layer

Strict version:

k+1 a block of layers is placed in the K a block in the layer.

conflict not hit: The cache is large enough that the strict placement policy makes the k+1 layer different objects mapped to K layer with a block caused by a miss.

Capacity not hit: The cache is not large enough to cause a miss.

4. Cache Management

L0: Compiler

L1,L2,L3: Hardware Logic

L4: Address translation hardware on the operating system +CPU

L5:AFS Client Process

6.4 Cache Memory

6.4.1 General-Purpose cache Memory Architecture

memory address: M bit

Cache Group: S=2s bit

each group of e Row Cache rows

1 per line a b=2b bytes of data block

A valid bit: Does this row make sense

Mark bit: t=m-(b+s) : A block that uniquely identifies a cache row

Cache Size C=s*e*b

Cache Address:

First, set the index, determine which group it is, then the marker bit, determine which line, and the last block offset.

T bits: Tag

s bit: Group Index

b bit: Block offset

6.4.2 Direct Map Cache

The cache is categorized by: The number of rows per group. Cache for each set of rows, called direct map cache.

1. Group selection in direct map cache

Extracts the corresponding S-bit group index bits of the destination address.

2. row matching in direct map cache

Valid bit &&t bit and target address mark match both true and hit

when not hit processing method: line substitution

The requested block is removed from the next layer, and then the group index in the block, and then the matching (valid, you can confirm that this object). Because the direct map cache has only one row per group, it is only necessary to replace the new row with the current row.

3. Direct mapping of word selection in the cache

The block offset provides the offset of the first byte of the desired word. As an example:

4. Synthesis

Describe the cache structure: (S,E,B,M)

Different blocks are mapped to the same group, which is distinguished by the marker bit

Take an example to understand the entire cache process

In this example, block 0, 4 maps to group 0, block 1,5 maps to group 1, Block 2, 6 to group 2, and block 3,7 to group 3.

1) Read address 0: Group 0 has not loaded any content in, so the valid bit is 0. A forced miss occurs. Cache remove block from the next layer 0. Block 0 is comprised of address 0 and address 12 parts.

2) Read address 1: hit.

3) Read address 13: belongs to block 6, Group 2. Force Miss, then read into block 6,m[12],m[13].

4) Read Address 8: belongs to block 4, group 0. Conflict not hit, group 0 is replaced by m[8],m[9].

5) Read address 0: belongs to block 0, group 0, conflict is not hit, group 0 is replaced with m[0],m[1]

5. Conflict misses in direct map cache

In this example, suppose the cache has only groups 0 and 12 groups, and one block is 16 bytes (4 array elements).

The program has a good spatial locality, but it still causes conflict misses. (This is because each group has only one row of this limit)

The first iteration of the application x[0], the group next is y[0]. Causes a conflict to miss. Each subsequent drink leads to a conflict-less hit.

Solution, change the code in X[8] to x[12], [8] to y[12]. This x[i],y[i] maps in different groups and resolves the problem. Such a method is called a padding of B-bytes after the array.

6.4.3 Group- linked cache

Because the direct mapping cache has conflicting misses, it relaxes the limit of only one row per group. The 1<e<c/b cache is called a group-linked cache.

1. group selection (as with direct map cache)

2. line matching and word selection (basically, just a few more rows)

3. Row substitution when group- linked cache misses

Which line to replace: 1. Random substitution

2. Using the local principle, replace the row with the lowest quoted probability (for example, most infrequently used, recently seldom used rows)

6.4.4 fully-connected cache

There is only one group that contains all the cache rows in the group.

1. Group selection . There is only one group, so there is no group index s=0. Address only two parts of tag and block offset

2. line matching word selection. same group as the cache.

Problems in teaching materials learning and the solving process

The number of hands-on parts of this week is less, and most of the content belongs to knowledge and understanding. There was some understanding of the memory hierarchy of the computer, but I didn't think it was so complicated and fine after reading the textbook.

Set of systems. It's easier to understand this part of the disk because it's more specific, but it's not quite understandable how the cache works, because there's some abstraction.

This week's code hosting

Code Link: https://git.oschina.net/929210354/Linux

Learning progress Bar /Cumulative) new/cumulative)
lines of code (newBlog volume (Learning time (new/cumulative) Important growth
Goal 5000 rows 30 Articles 400 hours
First week 0/0 1/2 10/10 Installing a Linux system using a virtual machine
Second week 341/341 1/3 20/30 Mastering the Core Linux commands
Third week 177/518 2/5 16/46 Learn VC programming on a virtual machine
Week Five 161/679 1/6 15/61
Week Six 73/752 1/7 15/76 The Y86 processor is installed
Seventh Week 134/886 1/8 12/88 Set up the project structure
    • "In-depth understanding of computer system V2" Learning Guide
    • Code-driven Programming learning
    • In-depth understanding of computer systems

20145239 "Information Security system Design Fundamentals" 7th Week Study Summary

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