20145307 "Information Security system design Fundamentals" Sixth Week study summary

20145307 "Information Security system design Fundamentals" Sixth Week study summarySummary of learning contents of textbookY86 Instruction Set architecture

Content: Defines an instruction set architecture that includes defining various state elements, instruction sets, and their encodings, a set of programming specifications, and exception event handling.

Programmer Visible State

Each instruction in the Y86 program reads or modifies portions of the processor state.

Y86 specifically includes: 8 program registers, 3 condition code ZF\SF\OF, program counter (PC).

The Y86 uses the virtual address to refer to the memory location. The last part of the program state is the status Code stat, which indicates the overall state of the program execution.

Y86 directive

A subset of the IA32 instruction set that includes only four-byte integer operations. There are fewer ways to address and fewer operations.

The instruction encoding length ranges from 1 bytes to 6 bytes, one instruction contains a single-byte instruction designator, may contain a single-byte register designator, and may contain a four-byte constant number. field FN Indicates an integer operation (OPL), Data movement condition (CMOVXX), or branch condition (JXX), all values are in hexadecimal notation

The call command returns the address to the stack and then jumps to the destination address. The RET instruction is returned from such a procedure call.

The PUSHL and POPL instructions are implemented into the stack and out of the stack.

Halt instruction to stop the execution of instructions. For Y86, executing the halt instruction will cause the processor to stop and set the status code to HLT.

Instruction encoding

The first byte of each instruction indicates the type of the instruction. This byte is divided into two parts, each part 4 bits: the height 4 bits is the code part, the low 4 bit is the function part. function values are only useful if a single set of related directives is shared with one code.

Each of the 8 program registers has a corresponding 0~7 register identifier, and the program register has a register file, which is a small, random-access memory with the Register ID as the address. The ID value 0xF is used when it is necessary to indicate that no registers should be accessed.

an important property of the instruction set: Byte encoding must have a unique explanation .

Y86 Exception Y86 Status code (in our design, any code other than AOK will stop the processor)

If the Y86 processor stops running instructions when an illegal instruction occurs, you can call an exception handler to make it more complete.

Y86 Program

The main difference between the Y86 code and the IA32 code:

Y86 may require more than one instruction to perform the functions performed by a IA32 instruction.

The Y86 does not have a scalable addressing mode.

The command indicates where the code or data should be placed, and how to align it. This program details the placement of stacks, initialization of data, initialization of programs, and the end of programs.

With "." The first word is the assembly command, which tells the assembler to adjust the address so that it can generate code or insert some data there.

The only tool for creating Y86 code is the assembler.

Instruction Set Simulator Yis:

Objective: To simulate the execution of Y86 machine code programs without attempting to simulate the behavior of any specific processor implementation.

Helps to debug programs before actual hardware is available, and also helps to check the results of simulated hardware or running programs on hardware.

Details of some Y86 directives

Most Y86 directives modify the state of a program in a straightforward way.

The behavior of the processor is not deterministic when executing the PUSHL and POPL directives because the registers to be placed on the stack are modified by the same instruction. There are usually two kinds of conventions:

Raw values for press-in/eject%ESP

Value after pressing in/eject%esp-/+4

Logic design and hardware control Language HCL

Three main components are required to achieve a digital system:

Combinatorial logic for calculating functions that operate on bits

Memory elements for storage bits

Clock signal to control memory element update

Logic gates

The output generated by the logic gates is a Boolean function that equals their input bit values. The logic gate operates only on the number of individual bits, not the entire word.

The logic gate is always active, and once the input of a gate changes, the output will change in a short time.

Combinational Circuits and HCl Boolean expressions

Combinational Circuits: A number of logic gates are combined into a single net that can be built into a computational block.

Multiplexing: Selects one from a different set of data signals based on the value of the input control signal.

There are two restrictions on the construction of these nets: (1) The outputs of two or more logic gates cannot be connected (2) The net must be non-ring.

The difference between an HCL expression and a logical expression in the C language:

The output of the combinational logic circuit will continue to respond to changes in the input; C expressions are evaluated only when they are encountered during program execution.

The logical expression of C allows the argument to be any integer, 0 for flase, and any other value to represent true, and the logical gate to manipulate only the bit values 0 and 1.

The logical expression of C may only be partially evaluated, and the logic gate simply responds to changes in the input, as there are no partial evaluation rules for the combinatorial logic.

Combination of Word-level circuits and HCl integer expressions

The combined power of a word-level calculation calculates the individual bits of the output word with a logic gate, based on each input word.

A line of medium-thick lines representing each bit of the carrying word, with dashed lines representing the result of a Boolean signal.

In the HCL, the multiplexed function is described by a condition expression.

Arithmetic/logic unit is a very important combination circuit.

Collection relationships

The general format for judging set relationships is:iexpr in {iexpr1，iexpr2，……，iexprk}

Memory and Clock

Storage devices are controlled by the same clock, and the two types of memory devices include:

Clock Register (register): a single bit or word is stored, and the input value is loaded with the clock signal control register.

Random access Storage (storage): Save multiple words, use the address to choose which word to read/write.

The registers in hardware and machine-level programming are slightly different, and are classified as "hardware registers" and "program registers".

The Y86 processor uses the clock register to save the program counter PC, the condition code cc, and the program status Stat.

The processor has a random access memory to store program data.

The processor also includes a separate read-only memory for reading instructions.

In most real-world systems, these two memories are combined into a two-port memory: one for reading instructions and one for reading or writing data.

Order of the Y86

Implement a SEQ Processor: On each clock cycle, SEQ executes all the steps required to process a complete instruction.

Organize the processing into stages

Perform actions at each stage and in each phase:

Fetch: Reads the instruction byte from the memory, the address is the value of the program counter PC

Decoding: Reads up to two operands from register to get Vala or valb

Execution: The arithmetic/logic unit either executes the operation specified by the instruction, calculates the valid address of the memory reference, or increases or decreases the stack pointer. The resulting value is Vale.

Access: Writes data to memory, or reads data from memory, and the readout value is Valm.

Write back: Up to two results can be written to the register file

Update PC: Set the PC as the address of the next instruction

The process required to execute an instruction is to execute the action indicated by the instruction, calculate the address, update the stack pointer, and determine the address of the next instruction.

For the handling of three control transfer commands: Note the bit signal CND. In the Update PC phase, check this flag, if this flag is 1, set the PC to Valc (jump target), if 0, set to Valp (the address of the next instruction).

SEQ Hardware structure

In SEQ, the processing of all hardware units is done in one clock cycle.

Drawing conventions for SEQ Route diagrams:

Light gray box indicates hardware unit

The control logic block is represented by a gray rounded rectangle.

The name of the line is indicated in the white ellipse.

A data connection with a width of length is expressed as a line of medium roughness

Data connections with a width of bytes or narrower are represented by a thin line

The connection of a single bit is indicated by a dashed line

Timing of SEQ

The SEQ implementation consists of a combination of logic and two types of memory devices:

Clock Register program counter and Condition code register

Random access memory register file, instruction memory, and data memory

Each clock cycle, the program counter will be installed in the new instruction address, only when the integer operation instruction is executed, the condition code register will be loaded, only when the RMMOVL, PUSHL or call instructions are executed, the data memory is written, and the two write ports of the register file allow two program registers to be updated per clock cycle.

Organization calculation principle: The processor never needs to read the state updated by the instruction in order to complete the execution of an instruction .

Clocks are used to control the updating of State elements, and values are propagated by combining logic.

Implementation of the SEQ phase

Take the finger stage:

Take the PC as the first byte of the address, read 6 bytes at a time.

icode: Control logic Block Calculation instructions

ifun: function code

Three-bit signals (calculated according to the Icode value): instr_valid : illegal instructions found;: need_regids contains register designator bytes; need_valC : include constant numbers?

The latter five bytes are the combined encoding of the Register designator byte and the constant number.

Decoding and writeback phases:

All need to access the register file, according to the case of four ports, determine which register should be read to generate the signal Vala, Valb.

Register file, supports simultaneous two reads and two writes, each port has an address connection (register ID) and a data connection (32 lines), can be used as the output word of the register file, but also as his input word.

Implementation phase:

Includes the arithmetic/logic unit (ALU), the output is the Vale signal. The ALU is usually used as an adder

Includes the Condition Code register

Each run produces: 0, sign, overflow, generate signal set_cc

Visit stage

Read or write program data

。 Two data blocks generate the memory address and the value of the memory input evidence, and two generate control signals indicating whether to read or write. When the read operation is performed, the data memory generates VALM.

Based on Icode,imem_error,instr_valid,dmem_error, the status code stat is calculated from the result of the instruction execution.

Update the PC stage to generate a new value for the program counter, depending on the type of instruction and whether to select the branch, the new PC may be valc, Valm, or Valp.

General principles of pipelining

An important feature of pipelining: Increases the throughput of the system, which is the total number of customers served per unit of time, but also slightly increases execution time, which is the time required to service a user.

Several important experiences in processor design:

Managing complexity is a top priority, keeping hardware design as simple as possible.

You do not need to implement ISA directly.

It is important to ensure that the design is correct at the outset.

A good start to creating a pipelined Y86 processor. However, the introduction of pipelining technology into a system with feedback can cause problems when the neighboring directives are related to their existence.

Pipeline control logic must handle the following 4 control scenarios, which are not handled by other mechanisms such as data forwarding and branch prediction:

Processing RET: The pipeline must be paused until the RET instruction reaches the writeback stage.

Load/Use adventure: pipelining must pause a cycle.

Branch predicting errors: Several instructions at the branch target are already in the pipeline before the branching logic finds that the branch should not be selected. These instructions must be removed from the pipeline.

Exception: When the-bar instruction causes an exception, we want to prohibit subsequent instructions from updating the visible state of the programmer, and leaned the exception instruction to the writeback phase, stopping execution.

problems encountered in the study

There are some problems in the book have not been understood, y86 simulator all smooth, hope tomorrow before the exam to understand.

20145307 "Information Security system design Fundamentals" Sixth Week study summary