2018-2019 20165219 summary of the fifth week of Information Security System Design Basics

2018-2019 20165219 Summary of storage technology in week 5 of Information Security System Design Basics

Random Access Memory: Comparison of SRAM and DRAM, traditional DRAM and enhanced dram

Enhanced DRAM:

Fast page mode DRAM: allows continuous access to the same row to get services directly from the row buffer.

Extended Data Output DRAM: Allows CAS signals to be more time-intensive.

Synchronous DRAM: SDRAM can output its supercell content faster than those of asynchronous memory.

Double Data Rate synchronization DRAM: It doubles DRAM by using two clock edges as control signals.

Video RAM: Used in the frame buffer of the Graphic System.

Non-volatile memory: stores their information even after power-off.

Disk Storage

Disk Structure

Disk capacity: the maximum number of BITs that can be recorded on a disk

Disk operations: Seek, seek time, rotate, rotate time, read

Logical Disk block: the disk controller reads data from a disk sector to the primary storage. The operating system sends a command to the disk controller to read a logical block number.

Locality

Temporal locality

Spatial locality

Locality of the command

Structural hierarchy of Storage

Generally, from the top to the bottom, the storage devices become slower, cheaper, and larger.

Cache in the Memory Hierarchy

In general, high-speed cache is a small and fast storage device that serves as a buffer area for data objects stored on larger and slower storage devices. The process of using high-speed cache is called cache.

Summary of the concept of memory hierarchies

In summary, cache-based memory hierarchies are effective because slow storage devices are cheaper, and programs tend to show locality: Time locality and space locality.

High-speed cache storage

General high-speed cache memory structure

In general, the cache structure can be described using tuples (S, E, B, m. The cache size (or capacity) C refers to the sum of the sizes of all blocks. The flag and valid bits are not included. Therefore, c = sEB.

Direct ing to high-speed cache

According to E (the number of high-speed cache lines in each group), high-speed cache is divided into different classes. Each group has only one row (E = 1) of high-speed cache called direct ing high-speed cache.

Group-connected high-speed cache

The problem caused by direct ing of conflicting cache hits is that each group has only one row, and the group-connected cache removes this restriction, therefore, each group saves an extra high-speed cache row.

Fully-connected high-speed cache

A fully-connected high-speed cache is composed of a group containing all the high-speed cache rows.

Summary of last week's incorrect questions

The () Directive in the Y86-64 does not perform memory access operations.

A.
Rrmovl

B.
Irmovq

C.
Rmmovq

D.
Pushq

E.
Jxx

F.
RET

Correct answer: A B E

2018-2019 20165219 summary of the fifth week of Information Security System Design Basics