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1.
The nor flash Address line is separated from the data line. The address and control signal are generated, and the data comes out.
The NAND flash Address line and the data line must be controlled by a program before data can be exported.
2.
Nandflash does not need to run the code. It is only used to store the code. norflash and SDRAM can directly run the code.
3. Start the Development Board
The CPU is automatically removed from the NAND Flash4 kb before readingThe data is stored in the in-chip SRAM (the S3C2440 is the SOC), and the in-chip SRAM is mapped to the space selected by the ngcs0 chip (that is, 0x00000000 ). The CPU is executed from 0x00000000, that is, the first 4 kb of content in NAND Flash.
Nor flash is mapped to the 0x00000000 address (ngcs0, which does not need in-chip SRAM to assist, so the starting address of the in-chip SRAM is still 0x40000000 ). then the CPU starts from 0x00000000 (that is, it is executed in norfalsh ).