32-bit CPU registers and 32-bit instructions

32-bit CPUs contain the following registers:

Four data registers (eax, EBX, ECx, and EDX)
2 address changes and pointer registers (ESI and EDI) 2 pointer registers (ESP and EBP)
Six segment registers (ES, Cs, SS, DS, FS, and GS)
1 Instruction Pointer register (EIP) 1 flag register (eflags)

1. Data Register
Data registers are mainly used to save information such as the operands and operation results, thus saving the time required to read the operands by occupying the bus and accessing the memory.
The 32-bit CPU has four 32-bit General registers eax, EBX, ECx, and EDX.
Access to low 16-bit data does not affect high 16-bit data.
These 16-bit low registers are named ax, BX, CX, and DX respectively, which are consistent with the registers in the previous CPU.
4 16-bit registers can be divided into 8 independent 8-bit registers (ax: Ah-Al, Bx: bh-BL, CX: ch-cl, DX: DH-DL ), each register has its own name and can be accessed independently.
Programmers can flexibly process the word/byte information by taking advantage of the "severable" feature of data registers.

The register eax is generally called an accumulator. operations performed with the accumulators may take less time. It can be used for multiplication, division, input/output, and other operations. It is frequently used;
Register EBX is called base register ). It can be used as a memory pointer;
Register ECx is called count register ).
During loop and string operations, use it to control the number of loops. during in-place operations, use Cl to specify the number of shifts when multiple bits are moved;
Register edX is called a data register ). During multiplication and division operations, it can be used as the default operand for calculation, or it can be used to store the port address of I/O.

In a 16-bit CPU, ax, BX, CX, and DX cannot be used as the base address and address change register to store the address of the storage unit,
In a 32-bit CPU, its 32-bit registers eax, EBX, ECx, and EDX not only can transmit data, but also store temporary data to save the Arithmetic Logic calculation results,
It can also be used as pointer registers, so these 32-bit registers are more universal.

2. Address Change register
The 32-bit CPU has two 32-bit General registers ESI and EDI.
Its Low 16 bits correspond to the Si and Di in the previous CPU, and its access to low 16 bits of data does not affect the high 16 bits of data.

Registers ESI, EDI, Si, and Di are called index register, which are mainly used to store the offset of the storage unit in the segment,
They can be used to address multiple storage operations and facilitate access to storage units in different addresses.
The address change register cannot be divided into eight-bit registers. As a general-purpose register, you can also store the operands and results of arithmetic logic operations.
They can be used as general memory pointers. In the execution of string operation commands, they have specific requirements and special features.

3. pointer register
Its Low 16 bits correspond to the BP and SP in the previous CPU, and its access to low 16 bits of data does not affect the high 16 bits of data.
The 32-bit CPU has two 32-bit General registers, EBP and ESP.
They are mainly used to access the storage units in the stack and stipulate that:
The EBP is used as the base pointer register to directly access data in the stack;
ESP is a stack pointer register that can only access the top of a stack.

Registers EBP, ESP, BP, and SP are known as pointer register and are mainly used to store the offset of the storage unit in the stack,
They can be used to address multiple storage operations and facilitate access to storage units in different addresses.
Pointer registers cannot be divided into eight-bit registers. As a general-purpose register, you can also store the operands and results of arithmetic logic operations.

4. segment register

Segment registers are set based on the management mode of memory segments. The physical address of the Memory Unit is composed of the segment register value and an offset.
In this way, two smaller-digit values can be combined into a memory address that can access a large physical space.
Segment registers inside the CPU:

ECS -- code segment register (code segment register); its value is the segment value of the code segment;
EDS-data segment register (data segment register), whose value is the segment value of the data segment;
Ees -- extra segment register; its value is the segment value of the additional data segment;
Ess -- stack segment register (stack segment register), whose value is the segment value of the stack segment;
EFS -- extra segment register; its value is the segment value of the additional data segment;
EGS -- extra segment register; its value is the segment value of the additional data segment.

In a 16-bit CPU system, it has only four segment registers. Therefore, the program can directly access up to four segments in use at any time.
In a microcomputer system, it has six segment registers. Therefore, programs developed in this environment can access up to six segments at the same time.

The 32-bit CPU has two different ways of working: real-time mode and protection mode. In each mode, segment registers have different functions. Simple Regulations
The ticket is described as follows:

Implementation Method: CS, DS, es, and SS of the first four segments are exactly the same as those of the previous CPU segments. The logic of the memory unit
The address is still in the format of "segment value: Offset. To access data in a memory segment, the offset between the register and the storage unit must be used.
Protection Mode: In this mode, the situation is much more complicated. The Block Value loaded into the segment register is not a segment value, but a value called "selector ..

5. Instruction Pointer register
The 32-bit CPU extends the instruction pointer to 32-bit and records it as an EIP. The 16-bit low of the EIP works the same as the IP address in the previous CPU.

The EIP and instruction pointer are the offsets of the commands to be executed next time in the code segment.
In a system with the prefetch command function, the command to be executed next time is usually prefetch into the command queue unless the transfer occurs.
Therefore, the command queue is not considered when you understand their functions.

6. Mark register

I. Operation Result flag
1. Carry mark CF (carry flag)
The carry mark CF is used to indicate whether the operation generates carry or borrow digits. If the highest bit of the calculation result produces a carry or borrow digit, the value is 1; otherwise, the value is 0.
This flag is used for addition and subtraction of the number of characters (in bytes), comparison of the number of unsigned values, and shift between words (in bytes, commands that specifically change the CF value.

2. Parity mark PF (parity flag)
The parity mark PF is used to reflect the parity of the number of "1" in the calculation result. If the number of "1" is an even number, the PF value is 1; otherwise, the value is 0.
PF can be used for parity check or to generate parity bits. In the process of data transmission, in order to provide the reliability of transmission, if the parity method is adopted, this flag can be used.

3. Auxiliary carry flag AF (Auxiliary carry flag)
In the following cases, the value of the secondary carry flag AF is set to 1; otherwise, the value is 0:

(1) When the word operation occurs, the lower byte is carried to the high byte or the borrow digit;
(2) When the byte operation occurs, the lower 4 bits are carried to the upper 4 bits or the borrow bits.
For the above 6 operation result flags, in general programming, flags CF, ZF, SF, and of are frequently used, the use frequency of flag pF and AF is low.

4. Zero flag (ZF)
The zero sign ZF is used to indicate whether the calculation result is 0. If the calculation result is 0, the value is 1; otherwise, the value is 0. You can use this flag when determining whether the calculation result is 0.

5. Sign SF (sign flag)
Symbol mark (SF) is the symbol bit used to reflect the calculation result. It is the same as the highest bit of the calculation result. In a microcomputer system, the number of symbols adopts the code representation. Therefore, SF also reflects the positive and negative numbers of the calculation results. When the calculation result is a positive number, the value of SF is 0; otherwise, the value is 1.

6. Overflow flag)
Overflow sign of indicates whether the result of the addition or subtraction operation of the number of symbols overflows. If the calculation result exceeds the range expressed by the current number of BITs, it is called overflow. The value of is set to 1. Otherwise, the value of is cleared to 0.

"Overflow" and "carry" are two different meanings. Do not confuse them. For details, refer to the relevant chapter in the computer composition principles course.

Ii. Status Control flag
The status control flags are used to control CPU operations. They must use special commands to change the status control flags.

1. Tracking mark TF (trap flag)
When the trace flag TF is set to 1, the CPU enters the single-step execution mode, that is, each execution of a command generates a single-step interruption request. This method is mainly used for program debugging.

There are no special commands in the command system to change the TF value of the flag, but the programmer can use other methods to change its value.

2. If (Interrupt-enable flag)
The interrupt flag if is used to determine whether the CPU responds to the interrupt requests that can be blocked outside the CPU.
However, no matter what the value of this sign is, the CPU must respond to the interrupt requests from the outside of the CPU that cannot be blocked and the interrupt requests generated inside the CPU.
The specific provisions are as follows:
(1) When if = 1, the CPU can respond to the interrupt requests externally blocked by the CPU;
(2) When if = 0, the CPU does not respond to the interrupt requests that can be blocked outside the CPU.
The CPU command system also has special commands to change the if value of the flag.

3. direction sign DF (Direction Flag)
The direction sign (DF) is used to determine the direction in which the pointer register is adjusted when the serial operation command is executed. Specific provisions are provided in section 5.2.11-string operation instructions.
In the microcomputer instruction system, special commands are also provided to change the value of the Flag DF.

3. 32-Bit Flag
1. iopl (I/O privilege level)
The I/O privileged flag is expressed by two binary bits, also known as an I/O privileged level field. This field specifies the privileged level required to execute the I/O command.
If the current privileged level is less than or equal to the iopl value, the I/O command can be executed. Otherwise, a protection exception occurs.

2. nested task flag NT (nested task)
The nested task flag NT is used to control the iret execution of the interrupt return command. The specific provisions are as follows:

(1) When Nt = 0, use the stored values in the stack to restore eflags, Cs, and EIP, and perform regular interrupted return operations;

(2) When Nt = 1, interrupt return is realized through task conversion.

3. Restart flag)
The restart mark RF is used to control whether debugging failures are accepted. NOTE: If RF is set to 0, the debugging fault is "accepted"; otherwise, the fault is rejected.
After successfully executing a command, the processor sets the RF to 0. When a non-debugging fault is received, the processor sets it to 1.

4. Virtual 8086 mode mark VM (Virtual 8086 Mode)
If the value of this flag is 1, it indicates that the processor is in the virtual 8086 mode. Otherwise, the processor is in the normal protection mode.

Assembly Instruction Set

 

The control registers Cr0, CR1, CR2, Cr 3, and system address registers GDTR, ldtr, idtr, and TR are newly added to the 80386 processor. They are all 32-bit.

 

For Cr0, the first PE mark is used to specify the working mode of the processor, and the last PG mark is used to specify whether the paging management mechanism is enabled for the processor. MP, em, ts, et are used to control the operations of the floating point coprocessor, the other bits are all 0. The low 16 bits of Cr0 are equivalent to 80286 of the machine status word MSW. The starting physical address of the page directory in the memory.
I. Common commands
1. General Data Transmission commands.
MoV transfers words or bytes.
Movsx first extends the symbol and then transmits it.
Movzx is not extended before transmission.
Push pushes words into the stack.
Pop pops up the word stack.
Pusha pushes ax, CX, dx, BX, SP, BP, Si, di into the stack in sequence.
Popa pops up the stack of DI, Si, BP, SP, BX, dx, CX, and ax in sequence.
Pushad pushes eax, ECx, EDX, EBX, ESP, EBP, ESI, and EDI to the stack in sequence.
Popad pops up the stacks of EDI, ESI, EBP, ESP, EBX, EDX, ECx, and eax in sequence.
Bswap swap the byte order in 32-bit registers
Xchg exchange word or byte. (at least one operand is a register, segment register cannot be used as the operand)
Cmpxchg compares and exchanges operands. (The second operand must be the accumulators Al/ax/eax)
Xadd switches and then accumulates (the result is in the first operand)
Xlat byte lookup conversion.
BX points to the starting point of a 256-byte table. Al indicates the index value of the table (0-255, that is, 0-ffh). The result of Al is returned as the table query result. ([bx + Al]-> Al)

2. input and output port transfer command.
In I/O port input. (Syntax: In accumulators, {port number │ DX })
Out I/O port output. (Syntax: out {port number │ DX}, accumulators)
The input and output ports are scheduled in the immediate mode. The value range is 0-255. The value range is 0-65535.
3. Destination Address Transfer command.
Load Lea to a valid address.
Example: Lea dx, string; Save the offset address to DX.
LDS transfers the target pointer and loads the pointer content into Ds.
For example: lDs Si, string; Save the segment address: Offset address to DS: Si.
Les transfers the target pointer and loads the pointer content into es.
For example, les Di and string; Save the segment address: Offset address to ESDI.
LFS transfers the target pointer and loads the pointer content into FS.
For example: LFS Di, string; Save the segment address: Offset address to FSD.
LGS transfers the target pointer and loads the pointer content into Gs.
For example: LGS Di, string; Save the segment address: Offset address to GSDI.
The LSS transfers the target pointer and loads the pointer content to the SS.
For example: LSS Di, string; Save the segment address: Offset address to SSDI.

4. Mark transfer command.
Transmit the lahf flag register and load the flag into ah.
Send the sahf flag register and load the ah content into the flag register.
Pushf marks the inbound stack.
Popf marks the exit of the stack.
Pushd 32-bit flag into the stack.
Popd 32-bit marks the stack.

Ii. arithmetic operation commands
Add addition.
Addition of ADC incoming bits.
INC plus 1.
ASCII code adjustment for AAA addition.
Decimal adjustment of DAA addition.
Sub subtraction.
SBB with borrow subtraction.
Dec minus 1.
NEC reverse (minus 0 ).
CMP comparison. (two operands are used as subtraction. Only the flag bit is modified and the result is not returned ).
ASCII code adjustment for AAS subtraction.
Decimal adjustment of the DAS subtraction.
Mul unsigned multiplication.
Imul integer multiplication.

The above two results are returned to Ah and Al (byte operation), or Dx and ax (word operation ),
AAM multiplication ASCII code adjustment.
Div unsigned division.
Idiv integer division.
The above two items are returned:
Commercial Al delivery, remainder ah, (byte operation );
Or commodity delivery ax, remainder delivery dx, (word operation ).

ASCII code adjustment for aad division.
CBW byte conversion into words (extend the byte symbols in Al to Ah)
The CWD character is converted to a dual character. (extend the character symbol in ax to DX)
Convert the cwde character to a dual character. (extend the word symbol in ax to eax)
CDQ dual-word extension. (extend the characters in eax to EDX)

Iii. Logic Operation commands
And and operation.
Or operation.
XOR exclusive or operation.
Not inverse.
Test. (two operands are used for operation. Only the flag bit is modified and the result is not returned ).
SHL logic shifts left.
Sal arithmetic shifts left. (= SHL)
The SHR logic is shifted to the right.
SAR arithmetic shift right (= SHR)
Rol loop shifts left.
Ror loop shifts right.
RCL shifts left through carry loop.
RCR shifts right through carry loop.
In the preceding eight shift commands, the number of shifts can reach 255.
During one shift, you can directly use the operation code, such as SHL ax, 1.
If one shift is performed, the CL registers the number of shifts.
For example, mov Cl, 04
SHL ax, Cl

Iv. String commands
DS: Si source string segment register: Source string address change.
Es I target string segment register: the address of the target string.
CX repeat count counter.
Al/ax scan value.
D sign 0 indicates that the Si and Di in the repeated operation should be automatically incremental; 1 indicates that the Si and Di should be automatically reduced.

The Z mark is used to control the end of a scan or comparison operation.
Movs string transmission.
(Movsb transfer character. movsw transfer word. movsd transfer dual word .)
CMPS string comparison.
(Cmpsb comparison character. cmpsw comparison word .)
SCAs string scan.
Compare the content of Al or ax with the target string, and the comparison result is reflected in the flag.
Lods Mount string.
Add the elements (words or bytes) in the source string to Al or ax one by one.
(Lodsb transfer character. lodsw transfer character. lodsd transfer dual character .)
STOs save string.
Is the lods inverse process.
Rep is repeated when CX/ECx <> 0.
Repe/repz is repeated when ZF = 1 or the comparison result is equal and CX/ECx <> 0.
Repne/repnz is repeated when ZF = 0 or the comparison results are not equal and CX/ECx <> 0.
Repc repeats when cf = 1 and CX/ECx <> 0.
Repnc repeats when cf = 0 and CX/ECx <> 0.

V. Program transfer instructions
1. Simple conditional transfer instruction
JZ (or je) OPR --------------- the result is zero transfer. test condition ZF = 1
Jnz (or JNE) OPR -------------- the result is not zero transfer. test condition ZF = 0
Js opr ---------------------- the result is negative transfer. test condition Sf = 1
Jns opr --------------------- the result is positive transfer. The test condition is Sf = 0.
Jo OPR --------------------- overflow transfer, test condition of =
Jno OPR -------------------- No overflow transfer, test condition Sf = 0
Jp opr ----------------------- the result is an even transfer. The test condition is Sf = 1.
Jnp OPR -------------------- the result is odd transfer, and the test condition Sf = 0
Jc opr -------------------- there is a bitwise transfer, test condition Sf = 1
Jnc opr -------------------- no carry transfer, test condition Sf = 0

2. Unsigned comparison condition transfer commands (the following commands are often cmp opd, And the commands after ops are transferred based on the comparison results)
JB (or jnae) OPD -------------- transfer if it is smaller than or not greater than or equal
JNB (or Jae) OPD --------------- transfer if it is not smaller than or greater than or equal
JA (or njbe) OPD --------------- transfer if the value is greater than or not less than or equal
JNA (or jbe) OPD --------------- transfer if it is not greater than or less than or equal

3. transfer command with symbol comparison Condition
JL (or jnge) -------------- transfer if it is less than or not greater than or equal
JNL (or jge) -------------- transfer if it is not smaller than or greater than or equal
JG (or njle) ------------- transfer if the value is greater than or not less than or equal
Jng (or jle) ------------- transfer if it is not greater than or less than or equal

6. Call subprograms and return commands
Call subroutine call command
RET subroutine return instruction

6. Other commands
Offset -------------------- returns the offset address.
SEG -------------------- return segment address
Equ (=) -------------------- equivalent statement
Purge -------------------- release statement
DUP -------------------- use the copy operator for the operand Field
Segment, ends -------------------- segment definition command
Assume -------------------- segment Address Allocation command
Org -------------------- command for starting offset Address Setting
$ -------------------- Current value of the address counter
Proc, endp -------------------- Process Definition Statement
Name, title, end -------------------- end of the program
Macro, endm -------------------- macro definition command
Xlat (translate) -------------------- code change command ----

VII. Condition signs
ZF zero sign -- when the result is negative, Sf = 1. Otherwise, Sf = 0.
AF secondary carry flag-the third digit in the calculation process has a bitwise value. Set af to 1. Otherwise, AF = 0.
PF parity flag ------ When the result operand contains an even number of "1", set pf to 1. Otherwise, pF = 0
SF symbol flag-when the result is negative, Sf = 1; otherwise, Sf = 0. Exceptions When Overflow
Cf carry mark ----- the highest valid bits generate carry value. For example, when an addition command is executed, MSB has an incoming bits and sets cf = 1; otherwise, cf = 0.
Of Overflow sign ----- if the result of the operand exceeds the range expressed by the machine, overflow occurs. If it is set to of = 1, otherwise, of = 0

 

8. Other commands: Refer to http://www.cnblogs.com/del/category/113560.html, or use the following commands