51 Single chip microcomputer interrupt system

51 Interrupt System

1. What is interruption

Interrupts are the state in which the CPU executes the program without the need for a pipe interrupt source, and the CPU goes to terminal processing when the interrupt source meets the interrupt trigger condition

2. Interrupt Source

80c51 A total of five interrupt sources are two external interrupt sources: INT0, INT1, two timer interrupt source T0, T1, one serial port interrupt source

Each interrupt source corresponds to an interrupt entry address

Interrupt Source	Entry Address
External interrupt Source INT0	0003H
Timer T0	000BH
External interrupt Source INT1	0013H
Timer T1	001BH
Serial Port Interrupt	0023H

3. Interrupt Control

3.1. Timing Control Register Tcon

Control Object	T1		T0		INT1		INT0
Bit order	D7	D6	D5	D4	D3	D2	D1	D0
Bit name	TF1	TR1	TF0	TR0	IE1	IT1	IE0	IT0

TF Timer Overflow Flag

TR Timer run Control bit

IE Interrupt Request Flag

IT Interrupt Trigger Mode: 1 o'clock falling edge trigger, 0 o'clock low level trigger

3.2. Serial Control Register Scon

D0 bit name RI send interrupt flag

D1 bit name is TI accept Interrupt flag

The corresponding D0 or D1 1 when receiving or sending a frame of data, and need to be reset in the Interrupt service program

3.3. Interrupt allow control register IE

Bit order	D7	D6	D5	D4	D3	D2	D1	D0
Bit name	Ea	/	/	Es	ET1	EX1	ET0	EX0

EA CPU interrupt total Allow bit

ES serial port interrupt allow bit

ET1 Timer 1 interrupt allow bit

EX1 external interrupt 1 allow bit

3.4. Interrupt Priority Control Register

Bit order	D7	D6	D5	D4	D3	D2	D1	D0
Bit name	/	/	/	Ps	PT1	PX1	PT0	PX0

PS Serial Port Interrupt Priority

PT Timer Interrupt Priority

PX External Interrupt Priority

A value of 1 is a high priority

A value of 0 is a low priority

4. Interrupt Handling Process

4.1. Sampling

Interrupt sampling occurs during the mid-s5p2 of each machine, the INT0 INT1 pin is detected, and the test results are set to IE0, IE1

If an interrupt is valid for a falling edge, the time of its high and low level is not less than one machine cycle

If the level is triggered, the effective signal is not less than one machine cycle

4.2. Enquiry

Each interrupt flag bit is queried sequentially during the S6 of each machine cycle, and interrupts are interrupted at the next machine cycle if there is an interrupt (load interrupt vector),

Interrupt Query Order: Ie0->tf0->ie1->tf1->ri and Ti

4.3. Response

4.3.1 response conditions

Interrupt source makes interrupt request, CPU on interrupt ea=1

Corresponding interrupt enable bit to turn on es,et1et0,ex1,ex0

No peer or more advanced Terminal Services, the current machine cycle is not the last cycle of the current instruction

4.3.2. Response

Includes two parts: breakpoint protection and Steering Interrupt program service entry.

Breakpoint Protection: Press the PC at the breakpoint location onto the stack

Assigning interrupt vectors to the PC

All hardware Auto-complete

4.3.3. Handling

Processing process

4.3.4. Response time

The duration from the interrupt Request flag position to the first instruction of the CPU executing the Terminal Services program

4.4. Return

The interrupt return instruction is Reti

Cannot be confused with RET at the end of the interrupt subroutine

5. Revocation of Interrupt Request

5.1. Timer counter CPU automatic revocation, no need to process

5.2. Serial port interrupt request requires re-interrupt program service inside Undo: such as CLR TI CLR RI

5.3. Revocation of external interrupt request

Pulse-triggered interrupts don't have to be considered

Interrupt on level requires the use of external hardware to revoke the request signal

51 Single chip microcomputer interrupt system